VLSI architecture design for a fast parallel label assignment in binary image
We propose a new connected component labeling method based on a 3/spl times/4 window for a binary image. This method possesses parallel processing to achieve high speed operation. According to the proposed method, we design an efficient VLSI architecture which only uses two process elements and a cl...
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| creator | Shyue-Wen Yang Ming-Hwa Sheu Hsien-Huang Wu Hung-En Chien Ping-Kuo Weng Ying-Yih Wu |
| description | We propose a new connected component labeling method based on a 3/spl times/4 window for a binary image. This method possesses parallel processing to achieve high speed operation. According to the proposed method, we design an efficient VLSI architecture which only uses two process elements and a class storage array to complete the whole label assignment after two raster scans. From experimental results, our design has better performance in terms of hardware cost and speed. This architecture has been verified on FPGA. It takes 6120 logic elements and its working frequency is about 80 MHz. |
| doi_str_mv | 10.1109/ISCAS.2005.1465107 |
| format | Conference Proceeding |
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It takes 6120 logic elements and its working frequency is about 80 MHz.</description><subject>Costs</subject><subject>Design methodology</subject><subject>Hardware</subject><subject>Labeling</subject><subject>Materials science and technology</subject><subject>Parallel processing</subject><subject>Pixel</subject><subject>Solid state circuits</subject><subject>Systolic arrays</subject><subject>Very large scale integration</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>9780780388345</isbn><isbn>0780388348</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotUM1OwzAYi_iRmEZfAC55gZbkS78mOU4VsEpFHApcp69NOoK6MqXlsLeniFmWfbFsyYzdSZFJKexD1ZSbJgMhMJN5gVLoC7YCiSaVCHjJEquNWKiMUTlesZUALdNcCbhhyTR9iQU5Kg3Fir181E3FKXafYfbd_BM9d34K-5H335ET72ma-ZEiDYMf-EDtojT9BQ5-nHkYeRtGiiceDrT3t-y6p2HyydnX7P3p8a3cpvXrc1Vu6jRIjXMKYIXXrUMDRJqEdoWxBLZ3VBCCcSiddAo63ebWOWOw6NqiV9IjWBCg1uz-vzd473fHuIzH0-58hvoFIQtQUw</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Shyue-Wen Yang</creator><creator>Ming-Hwa Sheu</creator><creator>Hsien-Huang Wu</creator><creator>Hung-En Chien</creator><creator>Ping-Kuo Weng</creator><creator>Ying-Yih Wu</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>VLSI architecture design for a fast parallel label assignment in binary image</title><author>Shyue-Wen Yang ; Ming-Hwa Sheu ; Hsien-Huang Wu ; Hung-En Chien ; Ping-Kuo Weng ; Ying-Yih Wu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-2290e7bd582aa7a07d689a29fda6a528d51d1d32c7b49dd8856cb6f31e5292023</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Costs</topic><topic>Design methodology</topic><topic>Hardware</topic><topic>Labeling</topic><topic>Materials science and technology</topic><topic>Parallel processing</topic><topic>Pixel</topic><topic>Solid state circuits</topic><topic>Systolic arrays</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Shyue-Wen Yang</creatorcontrib><creatorcontrib>Ming-Hwa Sheu</creatorcontrib><creatorcontrib>Hsien-Huang Wu</creatorcontrib><creatorcontrib>Hung-En Chien</creatorcontrib><creatorcontrib>Ping-Kuo Weng</creatorcontrib><creatorcontrib>Ying-Yih Wu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shyue-Wen Yang</au><au>Ming-Hwa Sheu</au><au>Hsien-Huang Wu</au><au>Hung-En Chien</au><au>Ping-Kuo Weng</au><au>Ying-Yih Wu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>VLSI architecture design for a fast parallel label assignment in binary image</atitle><btitle>2005 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2005</date><risdate>2005</risdate><spage>2393</spage><epage>2396 Vol. 3</epage><pages>2393-2396 Vol. 3</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>9780780388345</isbn><isbn>0780388348</isbn><abstract>We propose a new connected component labeling method based on a 3/spl times/4 window for a binary image. This method possesses parallel processing to achieve high speed operation. According to the proposed method, we design an efficient VLSI architecture which only uses two process elements and a class storage array to complete the whole label assignment after two raster scans. From experimental results, our design has better performance in terms of hardware cost and speed. This architecture has been verified on FPGA. It takes 6120 logic elements and its working frequency is about 80 MHz.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2005.1465107</doi></addata></record> |
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| identifier | ISSN: 0271-4302 |
| ispartof | 2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.2393-2396 Vol. 3 |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_ieee_primary_1465107 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Costs Design methodology Hardware Labeling Materials science and technology Parallel processing Pixel Solid state circuits Systolic arrays Very large scale integration |
| title | VLSI architecture design for a fast parallel label assignment in binary image |
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