Area and power efficient trellis computational blocks in 0.13/spl mu/m CMOS

Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a sili...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kamuf, M., Owall, V., Anderson, J.B.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Additive white noise CMOS process Computer architecture Convolutional codes Decoding Energy consumption Information technology Performance loss Silicon Viterbi algorithm
Online-Zugang:	Volltext bestellen
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