Area and power efficient trellis computational blocks in 0.13/spl mu/m CMOS
Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a sili...
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| container_end_page | 347 Vol. 1 |
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| creator | Kamuf, M. Owall, V. Anderson, J.B. |
| description | Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13/spl mu/m CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption. |
| doi_str_mv | 10.1109/ISCAS.2005.1464595 |
| format | Conference Proceeding |
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These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13/spl mu/m CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 9780780388345</identifier><identifier>ISBN: 0780388348</identifier><identifier>EISSN: 2158-1525</identifier><identifier>DOI: 10.1109/ISCAS.2005.1464595</identifier><language>eng</language><publisher>IEEE</publisher><subject>Additive white noise ; CMOS process ; Computer architecture ; Convolutional codes ; Decoding ; Energy consumption ; Information technology ; Performance loss ; Silicon ; Viterbi algorithm</subject><ispartof>2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.344-347 Vol. 1</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1464595$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1464595$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kamuf, M.</creatorcontrib><creatorcontrib>Owall, V.</creatorcontrib><creatorcontrib>Anderson, J.B.</creatorcontrib><title>Area and power efficient trellis computational blocks in 0.13/spl mu/m CMOS</title><title>2005 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13/spl mu/m CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption.</description><subject>Additive white noise</subject><subject>CMOS process</subject><subject>Computer architecture</subject><subject>Convolutional codes</subject><subject>Decoding</subject><subject>Energy consumption</subject><subject>Information technology</subject><subject>Performance loss</subject><subject>Silicon</subject><subject>Viterbi algorithm</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>9780780388345</isbn><isbn>0780388348</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9js1qwkAURi-1BUObF9DNfYEk82uSpQRFKaWLdC_T9AamTn6YiYhvbxauPXxwFt_mAKw4SzlnZXasq22dCsZ0ytVG6VK_QCS4LhKuhV5AXOYFmyeLQir9ChETOU-UZGIJcQj_bEZpmYtNBJ9bTwZN_4fjcCWP1La2sdRPOHlyzgZshm68TGayQ28c_rqhOQe0Pc4xMgujw-6SdVh9fdcf8NYaFyh--B3W-91PdUgsEZ1Gbzvjb6dHsnz-3gEnuUAD</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Kamuf, M.</creator><creator>Owall, V.</creator><creator>Anderson, J.B.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>Area and power efficient trellis computational blocks in 0.13/spl mu/m CMOS</title><author>Kamuf, M. ; Owall, V. ; Anderson, J.B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_14645953</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Additive white noise</topic><topic>CMOS process</topic><topic>Computer architecture</topic><topic>Convolutional codes</topic><topic>Decoding</topic><topic>Energy consumption</topic><topic>Information technology</topic><topic>Performance loss</topic><topic>Silicon</topic><topic>Viterbi algorithm</topic><toplevel>online_resources</toplevel><creatorcontrib>Kamuf, M.</creatorcontrib><creatorcontrib>Owall, V.</creatorcontrib><creatorcontrib>Anderson, J.B.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kamuf, M.</au><au>Owall, V.</au><au>Anderson, J.B.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Area and power efficient trellis computational blocks in 0.13/spl mu/m CMOS</atitle><btitle>2005 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2005</date><risdate>2005</risdate><spage>344</spage><epage>347 Vol. 1</epage><pages>344-347 Vol. 1</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>9780780388345</isbn><isbn>0780388348</isbn><abstract>Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13/spl mu/m CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2005.1464595</doi></addata></record> |
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| ispartof | 2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.344-347 Vol. 1 |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_ieee_primary_1464595 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Additive white noise CMOS process Computer architecture Convolutional codes Decoding Energy consumption Information technology Performance loss Silicon Viterbi algorithm |
| title | Area and power efficient trellis computational blocks in 0.13/spl mu/m CMOS |
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