Full-chip implementation of IDEALsmile on 90nm node devices with ArF lithography
Summary form only given. According to sizes dictated by ITRS roadmap, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. To overcome this issue Canon, in 2002, introduced a new technology, entitled lDEALSmile1i2 (Innovative Double Effecti...
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| creator | Yamazoe, K. Pepe, A. Kuno, T. Suzuki, A. Saitoh, K. Cantu, P. Capetti, G. Evangelista, E. Hasegawa, Y. Iwasa, J. Toublan, O. Loi, S. Lupo, M. |
| description | Summary form only given. According to sizes dictated by ITRS roadmap, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. To overcome this issue Canon, in 2002, introduced a new technology, entitled lDEALSmile1i2 (Innovative Double Effective source Aided Lithography with Single Mask Implemented Lithographic Enhancement), that was proven to be able to define contacts with high resolution and sufficiently large through pitch3 process window using a binary mask, cheap and simple to be manufactured, modified illumination and single exposure, without any negative impact on throughput and no increase of cost of ownership, The technology was further improved in 2003 with the introduction of Enhanced-IDEALSmile4 that, in certain conditions, allows achieving even higher contrast, and increased DOF thanks to three beam interference obtained with special shifted arrangement of dummy patterns without modifying optimized illumination shape. |
| doi_str_mv | 10.1109/IMNC.2004.245735 |
| format | Conference Proceeding |
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According to sizes dictated by ITRS roadmap, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. 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According to sizes dictated by ITRS roadmap, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. To overcome this issue Canon, in 2002, introduced a new technology, entitled lDEALSmile1i2 (Innovative Double Effective source Aided Lithography with Single Mask Implemented Lithographic Enhancement), that was proven to be able to define contacts with high resolution and sufficiently large through pitch3 process window using a binary mask, cheap and simple to be manufactured, modified illumination and single exposure, without any negative impact on throughput and no increase of cost of ownership, The technology was further improved in 2003 with the introduction of Enhanced-IDEALSmile4 that, in certain conditions, allows achieving even higher contrast, and increased DOF thanks to three beam interference obtained with special shifted arrangement of dummy patterns without modifying optimized illumination shape.</description><subject>Cost function</subject><subject>Graphics</subject><subject>Interference</subject><subject>Lighting</subject><subject>Lithography</subject><subject>Manufacturing processes</subject><subject>Optimized production technology</subject><subject>Throughput</subject><isbn>4990247205</isbn><isbn>9784990247201</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjEtPhDAURpsYE3WcvYmb_gHwlrZAlwQHJcHHYvaT23KRGl4B1My_l0S_zTk5i4-xOwGhEGAeypfXPIwAVBgpnUh9wW6UMRCpJAJ9xfbL8gnbpNFawDV7L766LnCtn7jvp456GlZc_TjwseHl4yGrlt53xLdgYOj5MNbEa_r2jhb-49eWZ3PBu03Gjxmn9nzLLhvsFtr_c8eOxeGYPwfV21OZZ1XgDawBCYuEwqCKpVGNs4ltpNbYWOckWR1HmCI0IjbWRDZGDWldG0QHLoU4Jblj93-3nohO0-x7nM8nobRRqZa_f31NVg</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Yamazoe, K.</creator><creator>Pepe, A.</creator><creator>Kuno, T.</creator><creator>Suzuki, A.</creator><creator>Saitoh, K.</creator><creator>Cantu, P.</creator><creator>Capetti, G.</creator><creator>Evangelista, E.</creator><creator>Hasegawa, Y.</creator><creator>Iwasa, J.</creator><creator>Toublan, O.</creator><creator>Loi, S.</creator><creator>Lupo, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2004</creationdate><title>Full-chip implementation of IDEALsmile on 90nm node devices with ArF lithography</title><author>Yamazoe, K. ; Pepe, A. ; Kuno, T. ; Suzuki, A. ; Saitoh, K. ; Cantu, P. ; Capetti, G. ; Evangelista, E. ; Hasegawa, Y. ; Iwasa, J. ; Toublan, O. ; Loi, S. ; Lupo, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-e1baea19a46394fcb7bf355afbcc3eb562a8a0f169b92b6a508dd9aac0c8068e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Cost function</topic><topic>Graphics</topic><topic>Interference</topic><topic>Lighting</topic><topic>Lithography</topic><topic>Manufacturing processes</topic><topic>Optimized production technology</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>Yamazoe, K.</creatorcontrib><creatorcontrib>Pepe, A.</creatorcontrib><creatorcontrib>Kuno, T.</creatorcontrib><creatorcontrib>Suzuki, A.</creatorcontrib><creatorcontrib>Saitoh, K.</creatorcontrib><creatorcontrib>Cantu, P.</creatorcontrib><creatorcontrib>Capetti, G.</creatorcontrib><creatorcontrib>Evangelista, E.</creatorcontrib><creatorcontrib>Hasegawa, Y.</creatorcontrib><creatorcontrib>Iwasa, J.</creatorcontrib><creatorcontrib>Toublan, O.</creatorcontrib><creatorcontrib>Loi, S.</creatorcontrib><creatorcontrib>Lupo, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yamazoe, K.</au><au>Pepe, A.</au><au>Kuno, T.</au><au>Suzuki, A.</au><au>Saitoh, K.</au><au>Cantu, P.</au><au>Capetti, G.</au><au>Evangelista, E.</au><au>Hasegawa, Y.</au><au>Iwasa, J.</au><au>Toublan, O.</au><au>Loi, S.</au><au>Lupo, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Full-chip implementation of IDEALsmile on 90nm node devices with ArF lithography</atitle><btitle>Digest of Papers. 2004 International Microprocesses and Nanotechnology Conference, 2004</btitle><stitle>IMNC</stitle><date>2004</date><risdate>2004</risdate><spage>86</spage><epage>86</epage><pages>86-86</pages><isbn>4990247205</isbn><isbn>9784990247201</isbn><abstract>Summary form only given. According to sizes dictated by ITRS roadmap, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. To overcome this issue Canon, in 2002, introduced a new technology, entitled lDEALSmile1i2 (Innovative Double Effective source Aided Lithography with Single Mask Implemented Lithographic Enhancement), that was proven to be able to define contacts with high resolution and sufficiently large through pitch3 process window using a binary mask, cheap and simple to be manufactured, modified illumination and single exposure, without any negative impact on throughput and no increase of cost of ownership, The technology was further improved in 2003 with the introduction of Enhanced-IDEALSmile4 that, in certain conditions, allows achieving even higher contrast, and increased DOF thanks to three beam interference obtained with special shifted arrangement of dummy patterns without modifying optimized illumination shape.</abstract><pub>IEEE</pub><doi>10.1109/IMNC.2004.245735</doi><tpages>1</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Cost function Graphics Interference Lighting Lithography Manufacturing processes Optimized production technology Throughput |
| title | Full-chip implementation of IDEALsmile on 90nm node devices with ArF lithography |
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