Fault and error models for VLSI
This paper describes a variety of fault and error models which are used as the basis for designing fault-tolerant Very Large Scale Integrated (VLSI) systems. The fault models describe physical defects and failures and the input patterns which will expose them, and are suitable for testing, while err...
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Veröffentlicht in: | Proc. IEEE; (United States) 1986-05, Vol.74 (5), p.639-654 |
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Format: | Artikel |
Sprache: | eng |
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