Parallel FPGA implementation of self-organizing maps

This paper presents an area-saving parallel implementation of a self-organizing map neural network (SOM) on FPGA. The purpose is to make available a finer grain of parallelism to be used in massively SIMD parallel SOM system architectures. We have handled a serial arithmetics (most significant bit f...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Ben Khalifa, K., Girau, B., Alexandre, F., Bedoui, M.H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Arithmetic Circuits Electroencephalography Field programmable gate arrays Humans Neural networks Neurons Programmable logic arrays Prototypes Self organizing feature maps
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