FPGA implementations of the ICEBERG block cipher

This paper presents FPGA (field programmable gate array) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Standaert, F.-X., Piret, G., Rouvroy, G., Quisquater, J.-J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Cryptography Electronic mail Feedback loop Field programmable gate arrays Hardware NIST Performance loss Software performance Table lookup Throughput
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