Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points
Circuit sizing (i.e., determining MOSFET channel widths and lengths which result in the most appropriate and robust circuit) is an optimization process. When it is completed, there always remains a dilemma; namely, whether a better solution exists. With different starting points one can arrive at di...
Gespeichert in:
| Veröffentlicht in: | Canadian journal of electrical and computer engineering 2003-07, Vol.28 (3/4), p.105-111 |
|---|---|
| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 111 |
|---|---|
| container_issue | 3/4 |
| container_start_page | 105 |
| container_title | Canadian journal of electrical and computer engineering |
| container_volume | 28 |
| creator | Puhan, J. Burmen, A. Tuma, T. |
| description | Circuit sizing (i.e., determining MOSFET channel widths and lengths which result in the most appropriate and robust circuit) is an optimization process. When it is completed, there always remains a dilemma; namely, whether a better solution exists. With different starting points one can arrive at different local minima. A heuristic process, consisting of many optimization runs starting from different initial points, is proposed. It tries to find another local minimum of the cost function in every run and thus reveals some additional information about the circuit. The mathematical background of the algorithm used is described. Finally, the heuristic algorithm is tested on some real integrated operating amplifier designs. The results show that from the cost-function point of view surprisingly many equivalent solutions exist. |
| doi_str_mv | 10.1109/CJECE.2003.1425097 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_1425097</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1425097</ieee_id><sourcerecordid>907942580</sourcerecordid><originalsourceid>FETCH-LOGICAL-c463t-fedb7ee1e07867a5d81b014afddd62c1eeae06265a16917f885ca64e7102c72e3</originalsourceid><addsrcrecordid>eNqF0U9LHDEYBvBQKnSrfoF6CT20XmabZDL5c5RlqxXBSz0PMfPO-srsZE0ylvrpm3EXCj3YUyD5vQ8veQj5xNmSc2a_ra7Xq_VSMFYvuRQNs_odWQhlZcW1qd-TBTOSVUYZ84F8TOmxQMMauSDbi9ENYTMBxTHDJroMHfUY_YSZJnzBcUN_YX6gCZ4huoGGXcYtvriMYaRxGhOd0oweYIqYMvpE-xALz3m-xhEzlrFdKPnphBz1bkhwejiPyd339c_VVXVze_ljdXFTeanqXPXQ3WsADkwbpV3TGX7PuHR913VKeA7ggCmhGseV5bo3pvFOSdCcCa8F1Mfk6z53F8PTBCm3W0wehsGNEKbUWqZt-SbDivzyphRGCsWl_T_URltjmwLP34RlR1FcSS308z_0MUyxFFLiOBemFnreUOyRjyGlCH27i7h18XdJaufy29fy27n89lB-GTrbDyEA_B04vP4B6aKsnA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>211283270</pqid></control><display><type>article</type><title>Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points</title><source>IEEE Electronic Library (IEL)</source><creator>Puhan, J. ; Burmen, A. ; Tuma, T.</creator><creatorcontrib>Puhan, J. ; Burmen, A. ; Tuma, T.</creatorcontrib><description>Circuit sizing (i.e., determining MOSFET channel widths and lengths which result in the most appropriate and robust circuit) is an optimization process. When it is completed, there always remains a dilemma; namely, whether a better solution exists. With different starting points one can arrive at different local minima. A heuristic process, consisting of many optimization runs starting from different initial points, is proposed. It tries to find another local minimum of the cost function in every run and thus reveals some additional information about the circuit. The mathematical background of the algorithm used is described. Finally, the heuristic algorithm is tested on some real integrated operating amplifier designs. The results show that from the cost-function point of view surprisingly many equivalent solutions exist.</description><identifier>ISSN: 0840-8688</identifier><identifier>EISSN: 2694-1783</identifier><identifier>DOI: 10.1109/CJECE.2003.1425097</identifier><identifier>CODEN: CJEEEL</identifier><language>eng</language><publisher>Montreal: IEEE Canada</publisher><subject>Algorithm design and analysis ; Amplifier design ; Analog integrated circuits ; Application specific integrated circuits ; Circuit simulation ; Circuits ; Computational modeling ; Computer simulation ; Design ; Design optimization ; Equations ; Equivalence ; Heuristic ; Humans ; Integrated circuits ; Mathematical models ; MOSFET circuits ; MOSFETs ; Optimization ; Robustness ; Sizing</subject><ispartof>Canadian journal of electrical and computer engineering, 2003-07, Vol.28 (3/4), p.105-111</ispartof><rights>Copyright IEEE Canada Jul-Oct 2003</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c463t-fedb7ee1e07867a5d81b014afddd62c1eeae06265a16917f885ca64e7102c72e3</citedby><cites>FETCH-LOGICAL-c463t-fedb7ee1e07867a5d81b014afddd62c1eeae06265a16917f885ca64e7102c72e3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1425097$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1425097$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Puhan, J.</creatorcontrib><creatorcontrib>Burmen, A.</creatorcontrib><creatorcontrib>Tuma, T.</creatorcontrib><title>Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points</title><title>Canadian journal of electrical and computer engineering</title><addtitle>J-CECE</addtitle><description>Circuit sizing (i.e., determining MOSFET channel widths and lengths which result in the most appropriate and robust circuit) is an optimization process. When it is completed, there always remains a dilemma; namely, whether a better solution exists. With different starting points one can arrive at different local minima. A heuristic process, consisting of many optimization runs starting from different initial points, is proposed. It tries to find another local minimum of the cost function in every run and thus reveals some additional information about the circuit. The mathematical background of the algorithm used is described. Finally, the heuristic algorithm is tested on some real integrated operating amplifier designs. The results show that from the cost-function point of view surprisingly many equivalent solutions exist.</description><subject>Algorithm design and analysis</subject><subject>Amplifier design</subject><subject>Analog integrated circuits</subject><subject>Application specific integrated circuits</subject><subject>Circuit simulation</subject><subject>Circuits</subject><subject>Computational modeling</subject><subject>Computer simulation</subject><subject>Design</subject><subject>Design optimization</subject><subject>Equations</subject><subject>Equivalence</subject><subject>Heuristic</subject><subject>Humans</subject><subject>Integrated circuits</subject><subject>Mathematical models</subject><subject>MOSFET circuits</subject><subject>MOSFETs</subject><subject>Optimization</subject><subject>Robustness</subject><subject>Sizing</subject><issn>0840-8688</issn><issn>2694-1783</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2003</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0U9LHDEYBvBQKnSrfoF6CT20XmabZDL5c5RlqxXBSz0PMfPO-srsZE0ylvrpm3EXCj3YUyD5vQ8veQj5xNmSc2a_ra7Xq_VSMFYvuRQNs_odWQhlZcW1qd-TBTOSVUYZ84F8TOmxQMMauSDbi9ENYTMBxTHDJroMHfUY_YSZJnzBcUN_YX6gCZ4huoGGXcYtvriMYaRxGhOd0oweYIqYMvpE-xALz3m-xhEzlrFdKPnphBz1bkhwejiPyd339c_VVXVze_ljdXFTeanqXPXQ3WsADkwbpV3TGX7PuHR913VKeA7ggCmhGseV5bo3pvFOSdCcCa8F1Mfk6z53F8PTBCm3W0wehsGNEKbUWqZt-SbDivzyphRGCsWl_T_URltjmwLP34RlR1FcSS308z_0MUyxFFLiOBemFnreUOyRjyGlCH27i7h18XdJaufy29fy27n89lB-GTrbDyEA_B04vP4B6aKsnA</recordid><startdate>20030701</startdate><enddate>20030701</enddate><creator>Puhan, J.</creator><creator>Burmen, A.</creator><creator>Tuma, T.</creator><general>IEEE Canada</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>H8D</scope></search><sort><creationdate>20030701</creationdate><title>Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points</title><author>Puhan, J. ; Burmen, A. ; Tuma, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c463t-fedb7ee1e07867a5d81b014afddd62c1eeae06265a16917f885ca64e7102c72e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Algorithm design and analysis</topic><topic>Amplifier design</topic><topic>Analog integrated circuits</topic><topic>Application specific integrated circuits</topic><topic>Circuit simulation</topic><topic>Circuits</topic><topic>Computational modeling</topic><topic>Computer simulation</topic><topic>Design</topic><topic>Design optimization</topic><topic>Equations</topic><topic>Equivalence</topic><topic>Heuristic</topic><topic>Humans</topic><topic>Integrated circuits</topic><topic>Mathematical models</topic><topic>MOSFET circuits</topic><topic>MOSFETs</topic><topic>Optimization</topic><topic>Robustness</topic><topic>Sizing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Puhan, J.</creatorcontrib><creatorcontrib>Burmen, A.</creatorcontrib><creatorcontrib>Tuma, T.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Aerospace Database</collection><jtitle>Canadian journal of electrical and computer engineering</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Puhan, J.</au><au>Burmen, A.</au><au>Tuma, T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points</atitle><jtitle>Canadian journal of electrical and computer engineering</jtitle><stitle>J-CECE</stitle><date>2003-07-01</date><risdate>2003</risdate><volume>28</volume><issue>3/4</issue><spage>105</spage><epage>111</epage><pages>105-111</pages><issn>0840-8688</issn><eissn>2694-1783</eissn><coden>CJEEEL</coden><abstract>Circuit sizing (i.e., determining MOSFET channel widths and lengths which result in the most appropriate and robust circuit) is an optimization process. When it is completed, there always remains a dilemma; namely, whether a better solution exists. With different starting points one can arrive at different local minima. A heuristic process, consisting of many optimization runs starting from different initial points, is proposed. It tries to find another local minimum of the cost function in every run and thus reveals some additional information about the circuit. The mathematical background of the algorithm used is described. Finally, the heuristic algorithm is tested on some real integrated operating amplifier designs. The results show that from the cost-function point of view surprisingly many equivalent solutions exist.</abstract><cop>Montreal</cop><pub>IEEE Canada</pub><doi>10.1109/CJECE.2003.1425097</doi><tpages>7</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0840-8688 |
| ispartof | Canadian journal of electrical and computer engineering, 2003-07, Vol.28 (3/4), p.105-111 |
| issn | 0840-8688 2694-1783 |
| language | eng |
| recordid | cdi_ieee_primary_1425097 |
| source | IEEE Electronic Library (IEL) |
| subjects | Algorithm design and analysis Amplifier design Analog integrated circuits Application specific integrated circuits Circuit simulation Circuits Computational modeling Computer simulation Design Design optimization Equations Equivalence Heuristic Humans Integrated circuits Mathematical models MOSFET circuits MOSFETs Optimization Robustness Sizing |
| title | Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T10%3A12%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Analogue%20integrated%20circuit%20sizing%20with%20several%20optimization%20runs%20using%20heuristics%20for%20setting%20initial%20points&rft.jtitle=Canadian%20journal%20of%20electrical%20and%20computer%20engineering&rft.au=Puhan,%20J.&rft.date=2003-07-01&rft.volume=28&rft.issue=3/4&rft.spage=105&rft.epage=111&rft.pages=105-111&rft.issn=0840-8688&rft.eissn=2694-1783&rft.coden=CJEEEL&rft_id=info:doi/10.1109/CJECE.2003.1425097&rft_dat=%3Cproquest_RIE%3E907942580%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=211283270&rft_id=info:pmid/&rft_ieee_id=1425097&rfr_iscdi=true |