SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep tran...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2005-04, Vol.40 (4), p.895-901
Hauptverfasser:	Zhang, K., Bhattacharya, U., Zhanping Chen, Hamzaoglu, F., Murray, D., Vallepalli, N., Yih Wang, Zheng, B., Bohr, M.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuit stability Circuits CMOS CMOS technology Degradation Design optimization Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuit technology Integrated circuits Integrated circuits by function (including memories and processors) Leakage Leakage reduction Power supplies Random access memory Reduction Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sleep sleep transistor SRAM Static random access memory Transistors Very large scale integration Voltage control weak-write test mode
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