Multiprocessor implementations of neural networks
Four methodologies were developed to explore the potential of using affordable multiprocessor computers to implement commercially available neural networks currently run on single processor systems. The methodologies-layer, cross-layer, pipeline, and hybrid-are based on a framework built around the...
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| creator | Bennington, R.W. DeClaris, N. |
| description | Four methodologies were developed to explore the potential of using affordable multiprocessor computers to implement commercially available neural networks currently run on single processor systems. The methodologies-layer, cross-layer, pipeline, and hybrid-are based on a framework built around the concepts of program decomposition, load balancing, communication overhead, and process synchronization. The methods were tested on a bus-based multiprocessor running two backpropagation network simulators, and the simulation results are reported. The pipeline and hybrid methods exhibited speedups of 1.6 and 1.9 per processor, respectively, for networks ranging in size from six to 20000 connections. These results indicate that it is possible to increase network simulation speeds and network size capabilities significantly.< > |
| doi_str_mv | 10.1109/ICSMC.1990.142120 |
| format | Conference Proceeding |
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The methodologies-layer, cross-layer, pipeline, and hybrid-are based on a framework built around the concepts of program decomposition, load balancing, communication overhead, and process synchronization. The methods were tested on a bus-based multiprocessor running two backpropagation network simulators, and the simulation results are reported. The pipeline and hybrid methods exhibited speedups of 1.6 and 1.9 per processor, respectively, for networks ranging in size from six to 20000 connections. These results indicate that it is possible to increase network simulation speeds and network size capabilities significantly.< ></description><identifier>ISBN: 9780879425975</identifier><identifier>ISBN: 0879425970</identifier><identifier>DOI: 10.1109/ICSMC.1990.142120</identifier><language>eng</language><publisher>IEEE</publisher><subject>Biomedical informatics ; Computer science ; Error correction ; Medical simulation ; Multiprocessing systems ; Network topology ; Neural networks ; Parallel processing ; Pipelines ; System testing</subject><ispartof>1990 IEEE International Conference on Systems, Man, and Cybernetics Conference Proceedings, 1990, p.323-325</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/142120$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/142120$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bennington, R.W.</creatorcontrib><creatorcontrib>DeClaris, N.</creatorcontrib><title>Multiprocessor implementations of neural networks</title><title>1990 IEEE International Conference on Systems, Man, and Cybernetics Conference Proceedings</title><addtitle>ICSMC</addtitle><description>Four methodologies were developed to explore the potential of using affordable multiprocessor computers to implement commercially available neural networks currently run on single processor systems. The methodologies-layer, cross-layer, pipeline, and hybrid-are based on a framework built around the concepts of program decomposition, load balancing, communication overhead, and process synchronization. The methods were tested on a bus-based multiprocessor running two backpropagation network simulators, and the simulation results are reported. The pipeline and hybrid methods exhibited speedups of 1.6 and 1.9 per processor, respectively, for networks ranging in size from six to 20000 connections. These results indicate that it is possible to increase network simulation speeds and network size capabilities significantly.< ></description><subject>Biomedical informatics</subject><subject>Computer science</subject><subject>Error correction</subject><subject>Medical simulation</subject><subject>Multiprocessing systems</subject><subject>Network topology</subject><subject>Neural networks</subject><subject>Parallel processing</subject><subject>Pipelines</subject><subject>System testing</subject><isbn>9780879425975</isbn><isbn>0879425970</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1990</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81KxDAUhQMiKGMfQFd9gY65-elNllL8GZhhFup6COktRNumJBnEt7cwns3H4YMDh7F74FsAbh933fuh24K1a1cCBL9ilUXDDVoltEV9w6qcv_gapYFzecvgcB5LWFL0lHNMdZiWkSaaiyshzrmOQz3TOblxRfmJ6TvfsevBjZmqf27Y58vzR_fW7I-vu-5p3wRAURoHEgxoQ8IZ7dzgnbItWO-tBI-DbF3LEcG3qASqHo1E3XPfY49Iq5Mb9nDZDUR0WlKYXPo9XX7JPwUpQwU</recordid><startdate>1990</startdate><enddate>1990</enddate><creator>Bennington, R.W.</creator><creator>DeClaris, N.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1990</creationdate><title>Multiprocessor implementations of neural networks</title><author>Bennington, R.W. ; DeClaris, N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-a1318158e2a85aafca49619cc931c7f36a60771c674274d78375d0cd7d77ea603</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1990</creationdate><topic>Biomedical informatics</topic><topic>Computer science</topic><topic>Error correction</topic><topic>Medical simulation</topic><topic>Multiprocessing systems</topic><topic>Network topology</topic><topic>Neural networks</topic><topic>Parallel processing</topic><topic>Pipelines</topic><topic>System testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Bennington, R.W.</creatorcontrib><creatorcontrib>DeClaris, N.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bennington, R.W.</au><au>DeClaris, N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Multiprocessor implementations of neural networks</atitle><btitle>1990 IEEE International Conference on Systems, Man, and Cybernetics Conference Proceedings</btitle><stitle>ICSMC</stitle><date>1990</date><risdate>1990</risdate><spage>323</spage><epage>325</epage><pages>323-325</pages><isbn>9780879425975</isbn><isbn>0879425970</isbn><abstract>Four methodologies were developed to explore the potential of using affordable multiprocessor computers to implement commercially available neural networks currently run on single processor systems. The methodologies-layer, cross-layer, pipeline, and hybrid-are based on a framework built around the concepts of program decomposition, load balancing, communication overhead, and process synchronization. The methods were tested on a bus-based multiprocessor running two backpropagation network simulators, and the simulation results are reported. The pipeline and hybrid methods exhibited speedups of 1.6 and 1.9 per processor, respectively, for networks ranging in size from six to 20000 connections. These results indicate that it is possible to increase network simulation speeds and network size capabilities significantly.< ></abstract><pub>IEEE</pub><doi>10.1109/ICSMC.1990.142120</doi><tpages>3</tpages></addata></record> |
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| identifier | ISBN: 9780879425975 |
| ispartof | 1990 IEEE International Conference on Systems, Man, and Cybernetics Conference Proceedings, 1990, p.323-325 |
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| language | eng |
| recordid | cdi_ieee_primary_142120 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Biomedical informatics Computer science Error correction Medical simulation Multiprocessing systems Network topology Neural networks Parallel processing Pipelines System testing |
| title | Multiprocessor implementations of neural networks |
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