3D graphics circuits for 3G multimedia terminals

Summary form only given. The development of system-on-chip technology drives various multimedia and even 3D graphics capabilities into 3G multimedia terminals. The 3D applications are attractive to the mobile market, however, implementing them requires a huge amount of parallel calculations and memo...

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description Summary form only given. The development of system-on-chip technology drives various multimedia and even 3D graphics capabilities into 3G multimedia terminals. The 3D applications are attractive to the mobile market, however, implementing them requires a huge amount of parallel calculations and memory bandwidth within the boundary of limited battery power. In this talk, we discuss 'how to' and 'where to' apply various circuits and architecture techniques to the 3D graphics pipeline to achieve low power consumption, with the example of RAMP (RAM processor) by KAIST research group and several other world-class mobile 3D engines.
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ispartof 2004 International Symposium on System-on-Chip, 2004. Proceedings, 2004, p.205
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Bandwidth
Batteries
Circuits
Energy consumption
Graphics
Multimedia systems
Pipelines
Random access memory
Read-write memory
System-on-a-chip
title 3D graphics circuits for 3G multimedia terminals
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