A technique for designing totally self-checking domino logic circuits
A scheme for concurrent self-checking domino logic circuit is proposed. The self-checking feature is achieved by transistor sharing of the original and its inverse functions and by using the outputs as 1-out-of-2 code. The sharing of transistors lowers the overhead required for the inverse function....
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| creator | Tang, C.K. Lata, P.K. Parkerson, J.P. |
| description | A scheme for concurrent self-checking domino logic circuit is proposed. The self-checking feature is achieved by transistor sharing of the original and its inverse functions and by using the outputs as 1-out-of-2 code. The sharing of transistors lowers the overhead required for the inverse function. A checker circuit is embedded into the self-checking implementation. The scheme is especially suitable for large CMOS domino logic circuits. |
| doi_str_mv | 10.1109/ISQED.2005.14 |
| format | Conference Proceeding |
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The scheme is especially suitable for large CMOS domino logic circuits.</description><subject>Circuit faults</subject><subject>CMOS logic circuits</subject><subject>Electrical fault detection</subject><subject>Encoding</subject><subject>Fault detection</subject><subject>Logic circuits</subject><subject>Logic functions</subject><subject>Logic testing</subject><subject>Monitoring</subject><subject>Very large scale integration</subject><issn>1948-3287</issn><issn>1948-3295</issn><isbn>9780769523019</isbn><isbn>0769523013</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9jEtLw0AURgcfYK1dunIzfyDx3nlkZpaltlooiNh9CTd30tE00SRd9N-rKK4-OIfzCXGLkCNCuF-_viwfcgVgczRnYoLB-EyrYM_FLDgPrghWacBw8e-8uxLXw_AGYKx1fiKWczky7dv0eWQZu15WPKS6TW0tx24sm-YkB25iRnum9x9adYfUdrLp6kSSUk_HNA434jKWzcCzv52K7Wq5XTxlm-fH9WK-yRI6O2aaQuRgKVQKMKJjIMVKFRWpQGhKbX2sykobryJAiVAYzYTBW_yuSE_F3e9tYubdR58OZX_aoUGwDvQXwP5MUA</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Tang, C.K.</creator><creator>Lata, P.K.</creator><creator>Parkerson, J.P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2005</creationdate><title>A technique for designing totally self-checking domino logic circuits</title><author>Tang, C.K. ; Lata, P.K. ; Parkerson, J.P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-3c9fe95c9d201f17e0c2e226dc29c14a358fdad3482f00a10643ec1985195cc3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Circuit faults</topic><topic>CMOS logic circuits</topic><topic>Electrical fault detection</topic><topic>Encoding</topic><topic>Fault detection</topic><topic>Logic circuits</topic><topic>Logic functions</topic><topic>Logic testing</topic><topic>Monitoring</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Tang, C.K.</creatorcontrib><creatorcontrib>Lata, P.K.</creatorcontrib><creatorcontrib>Parkerson, J.P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tang, C.K.</au><au>Lata, P.K.</au><au>Parkerson, J.P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A technique for designing totally self-checking domino logic circuits</atitle><btitle>Sixth international symposium on quality electronic design (isqed'05)</btitle><stitle>ISQED</stitle><date>2005</date><risdate>2005</risdate><spage>128</spage><epage>132</epage><pages>128-132</pages><issn>1948-3287</issn><eissn>1948-3295</eissn><isbn>9780769523019</isbn><isbn>0769523013</isbn><abstract>A scheme for concurrent self-checking domino logic circuit is proposed. The self-checking feature is achieved by transistor sharing of the original and its inverse functions and by using the outputs as 1-out-of-2 code. The sharing of transistors lowers the overhead required for the inverse function. A checker circuit is embedded into the self-checking implementation. The scheme is especially suitable for large CMOS domino logic circuits.</abstract><pub>IEEE</pub><doi>10.1109/ISQED.2005.14</doi><tpages>5</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit faults CMOS logic circuits Electrical fault detection Encoding Fault detection Logic circuits Logic functions Logic testing Monitoring Very large scale integration |
| title | A technique for designing totally self-checking domino logic circuits |
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