An instruction set architecture based code compression scheme for embedded processors

Summary form only given. We propose a general purpose code compression scheme for embedded systems, based on the instruction set architecture and report results on the Intel StrongARM, a low-cost, low-power RISC architecture and TI TMS320C62x, a widely used VLIW architecture. Fast decompression tech...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Menon, S.K., Shankar, P.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automation Computer architecture Computer science Data compression Decoding Dictionaries Embedded system Hamming distance Reduced instruction set computing VLIW
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!