A design for test technique for parametric analysis of SRAM: on-die low yield analysis
Parametric analysis of microprocessor SRAM through special design for test features (DFT) is used extensively by fault isolation and failure analysis engineers to find and characterize defects. Unfortunately, a growing amount of leakage on each new process is distorting these low yield analysis (LYA...
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| creator | Mauck, B.M. Ravichandran, V. Mughal, U.A. |
| description | Parametric analysis of microprocessor SRAM through special design for test features (DFT) is used extensively by fault isolation and failure analysis engineers to find and characterize defects. Unfortunately, a growing amount of leakage on each new process is distorting these low yield analysis (LYA) testmode l-V curves, making it increasingly difficult to find and differentiate defects. The goal of This work is to discuss the simulation and silicon results of a concept on-die LYA (ODLYA) circuit implemented in a 65 nm CMOS process technology. ODLYA is used to curve-trace individual transistors within an SRAM cell and read out results in an automated fashion. Taking measurements on-die eliminates interconnect-dominated IR drop and leakage distortion from several levels of multiplexing. The proposed implementation enables non-destructive high-speed parametric analysis with less dependency on growing cache sizes, number of cores, and scaling process technologies. |
| doi_str_mv | 10.1109/TEST.2004.1386942 |
| format | Conference Proceeding |
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Unfortunately, a growing amount of leakage on each new process is distorting these low yield analysis (LYA) testmode l-V curves, making it increasingly difficult to find and differentiate defects. The goal of This work is to discuss the simulation and silicon results of a concept on-die LYA (ODLYA) circuit implemented in a 65 nm CMOS process technology. ODLYA is used to curve-trace individual transistors within an SRAM cell and read out results in an automated fashion. Taking measurements on-die eliminates interconnect-dominated IR drop and leakage distortion from several levels of multiplexing. The proposed implementation enables non-destructive high-speed parametric analysis with less dependency on growing cache sizes, number of cores, and scaling process technologies.</description><identifier>ISBN: 0780385802</identifier><identifier>ISBN: 9780780385801</identifier><identifier>DOI: 10.1109/TEST.2004.1386942</identifier><language>eng</language><publisher>Piscataway NJ: IEEE</publisher><subject>Applied sciences ; Circuit faults ; Circuit simulation ; Circuit testing ; CMOS process ; Design engineering ; Design for testability ; Design. Technologies. Operation analysis. Testing ; Electronics ; Exact sciences and technology ; Failure analysis ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Microprocessors ; Random access memory ; Semiconductor electronics. Microelectronics. Optoelectronics. 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Unfortunately, a growing amount of leakage on each new process is distorting these low yield analysis (LYA) testmode l-V curves, making it increasingly difficult to find and differentiate defects. The goal of This work is to discuss the simulation and silicon results of a concept on-die LYA (ODLYA) circuit implemented in a 65 nm CMOS process technology. ODLYA is used to curve-trace individual transistors within an SRAM cell and read out results in an automated fashion. Taking measurements on-die eliminates interconnect-dominated IR drop and leakage distortion from several levels of multiplexing. The proposed implementation enables non-destructive high-speed parametric analysis with less dependency on growing cache sizes, number of cores, and scaling process technologies.</description><subject>Applied sciences</subject><subject>Circuit faults</subject><subject>Circuit simulation</subject><subject>Circuit testing</subject><subject>CMOS process</subject><subject>Design engineering</subject><subject>Design for testability</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Failure analysis</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Microprocessors</subject><subject>Random access memory</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon</subject><subject>Testing, measurement, noise and reliability</subject><subject>Transistors</subject><isbn>0780385802</isbn><isbn>9780780385801</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkE9LAzEQxQMiqLUfQLzk4nHrJGmyibdS6h9QBFu9ltlkopHtbt2sSL-9ixV9hzfw3o85PMbOBEyEAHe5WixXEwkwnQhljZvKA3YCpQVltQV5xMY5v8Mg5Ywx-pi9zHignF4bHtuO95T7wfxbkz4-6SfaYocb6rvkOTZY73LKvI18-TR7uOJtU4REvG6_-C5RHf6QU3YYsc40_r0j9ny9WM1vi_vHm7v57L5IEnRfBONRQxAenYNKeFkpERWgkzZQjCXIKpRTXWlRlT5aV8UoyJADDMrBgI7Yxf7vFrPHOnbY-JTX2y5tsNuthTVKKC0G7nzPJSL6r_cTqW_mYlya</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Mauck, B.M.</creator><creator>Ravichandran, V.</creator><creator>Mughal, U.A.</creator><general>IEEE</general><general>International Test Conference</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>IQODW</scope></search><sort><creationdate>2004</creationdate><title>A design for test technique for parametric analysis of SRAM: on-die low yield analysis</title><author>Mauck, B.M. ; Ravichandran, V. ; Mughal, U.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i205t-d6ca50d1ca990b1c2b31f30a928deff702bd745b51b7cf89bff1e6e90ad3901f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Applied sciences</topic><topic>Circuit faults</topic><topic>Circuit simulation</topic><topic>Circuit testing</topic><topic>CMOS process</topic><topic>Design engineering</topic><topic>Design for testability</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Failure analysis</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Microprocessors</topic><topic>Random access memory</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon</topic><topic>Testing, measurement, noise and reliability</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Mauck, B.M.</creatorcontrib><creatorcontrib>Ravichandran, V.</creatorcontrib><creatorcontrib>Mughal, U.A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mauck, B.M.</au><au>Ravichandran, V.</au><au>Mughal, U.A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A design for test technique for parametric analysis of SRAM: on-die low yield analysis</atitle><btitle>2004 International Conferce on Test</btitle><stitle>TEST</stitle><date>2004</date><risdate>2004</risdate><spage>105</spage><epage>113</epage><pages>105-113</pages><isbn>0780385802</isbn><isbn>9780780385801</isbn><abstract>Parametric analysis of microprocessor SRAM through special design for test features (DFT) is used extensively by fault isolation and failure analysis engineers to find and characterize defects. Unfortunately, a growing amount of leakage on each new process is distorting these low yield analysis (LYA) testmode l-V curves, making it increasingly difficult to find and differentiate defects. The goal of This work is to discuss the simulation and silicon results of a concept on-die LYA (ODLYA) circuit implemented in a 65 nm CMOS process technology. ODLYA is used to curve-trace individual transistors within an SRAM cell and read out results in an automated fashion. Taking measurements on-die eliminates interconnect-dominated IR drop and leakage distortion from several levels of multiplexing. The proposed implementation enables non-destructive high-speed parametric analysis with less dependency on growing cache sizes, number of cores, and scaling process technologies.</abstract><cop>Piscataway NJ</cop><cop>Washington DC</cop><pub>IEEE</pub><doi>10.1109/TEST.2004.1386942</doi><tpages>9</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 0780385802 |
| ispartof | 2004 International Conferce on Test, 2004, p.105-113 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Applied sciences Circuit faults Circuit simulation Circuit testing CMOS process Design engineering Design for testability Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Failure analysis Integrated circuits Integrated circuits by function (including memories and processors) Microprocessors Random access memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Testing, measurement, noise and reliability Transistors |
| title | A design for test technique for parametric analysis of SRAM: on-die low yield analysis |
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