A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hi...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2005-01, Vol.40 (1), p.245-253
Hauptverfasser:	Noda, H., Inoue, K., Kuroiwa, M., Igaue, F., Yamamoto, K., Mattausch, H.J., Koide, T., Amo, A., Hachisuka, A., Soeda, S., Hayashi, I., Morishita, F., Dosaka, K., Arimoto, K., Fujishima, K., Anami, K., Yoshihara, T.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Architecture Arrays CADCAM Chip formation Chips Circuits CMOS memory integrated circuits Computer aided manufacturing Costs Design. Technologies. Operation analysis. Testing Dynamics Electronics embedded DRAM Exact sciences and technology Integrated circuit yield Integrated circuits Integrated circuits by function (including memories and processors) Large-scale systems network Power dissipation Random access memory Redundancy Searching Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon ternary CAM Yield estimation
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