A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture
This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hi...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2005-01, Vol.40 (1), p.245-253 |
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| creator | Noda, H. Inoue, K. Kuroiwa, M. Igaue, F. Yamamoto, K. Mattausch, H.J. Koide, T. Amo, A. Hachisuka, A. Soeda, S. Hayashi, I. Morishita, F. Dosaka, K. Arimoto, K. Fujishima, K. Anami, K. Yoshihara, T. |
| description | This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips. |
| doi_str_mv | 10.1109/JSSC.2004.838016 |
| format | Article |
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A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2004.838016</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Architecture ; Arrays ; CADCAM ; Chip formation ; Chips ; Circuits ; CMOS memory integrated circuits ; Computer aided manufacturing ; Costs ; Design. Technologies. Operation analysis. Testing ; Dynamics ; Electronics ; embedded DRAM ; Exact sciences and technology ; Integrated circuit yield ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Large-scale systems ; network ; Power dissipation ; Random access memory ; Redundancy ; Searching ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Silicon ; ternary CAM ; Yield estimation</subject><ispartof>IEEE journal of solid-state circuits, 2005-01, Vol.40 (1), p.245-253</ispartof><rights>2005 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2005</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c384t-94fd6e16cff1fd735c8b08e27e4309d42533e0a39c4fd16c35a8b08b711c14e23</citedby><cites>FETCH-LOGICAL-c384t-94fd6e16cff1fd735c8b08e27e4309d42533e0a39c4fd16c35a8b08b711c14e23</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1375008$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,792,4036,4037,23909,23910,25118,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1375008$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=16476471$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Noda, H.</creatorcontrib><creatorcontrib>Inoue, K.</creatorcontrib><creatorcontrib>Kuroiwa, M.</creatorcontrib><creatorcontrib>Igaue, F.</creatorcontrib><creatorcontrib>Yamamoto, K.</creatorcontrib><creatorcontrib>Mattausch, H.J.</creatorcontrib><creatorcontrib>Koide, T.</creatorcontrib><creatorcontrib>Amo, A.</creatorcontrib><creatorcontrib>Hachisuka, A.</creatorcontrib><creatorcontrib>Soeda, S.</creatorcontrib><creatorcontrib>Hayashi, I.</creatorcontrib><creatorcontrib>Morishita, F.</creatorcontrib><creatorcontrib>Dosaka, K.</creatorcontrib><creatorcontrib>Arimoto, K.</creatorcontrib><creatorcontrib>Fujishima, K.</creatorcontrib><creatorcontrib>Anami, K.</creatorcontrib><creatorcontrib>Yoshihara, T.</creatorcontrib><title>A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.</description><subject>Applied sciences</subject><subject>Architecture</subject><subject>Arrays</subject><subject>CADCAM</subject><subject>Chip formation</subject><subject>Chips</subject><subject>Circuits</subject><subject>CMOS memory integrated circuits</subject><subject>Computer aided manufacturing</subject><subject>Costs</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Dynamics</subject><subject>Electronics</subject><subject>embedded DRAM</subject><subject>Exact sciences and technology</subject><subject>Integrated circuit yield</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Large-scale systems</subject><subject>network</subject><subject>Power dissipation</subject><subject>Random access memory</subject><subject>Redundancy</subject><subject>Searching</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Technologies. Operation analysis. Testing</topic><topic>Dynamics</topic><topic>Electronics</topic><topic>embedded DRAM</topic><topic>Exact sciences and technology</topic><topic>Integrated circuit yield</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Large-scale systems</topic><topic>network</topic><topic>Power dissipation</topic><topic>Random access memory</topic><topic>Redundancy</topic><topic>Searching</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. 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A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2004.838016</doi><tpages>9</tpages></addata></record> |
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| subjects | Applied sciences Architecture Arrays CADCAM Chip formation Chips Circuits CMOS memory integrated circuits Computer aided manufacturing Costs Design. Technologies. Operation analysis. Testing Dynamics Electronics embedded DRAM Exact sciences and technology Integrated circuit yield Integrated circuits Integrated circuits by function (including memories and processors) Large-scale systems network Power dissipation Random access memory Redundancy Searching Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon ternary CAM Yield estimation |
| title | A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture |
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