A low-power Booth multiplier using novel data partition method
The Booth algorithm has a characteristic that the Booth algorithm produces the Booth encoded products with a value of zero when input data stream have sequentially equal values. Therefore, partial products have greater chances of being zero when the one with a smaller dynamic range of two inputs is...
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creator | Jongsu Park San Kim Yong-Surk Lee |
description | The Booth algorithm has a characteristic that the Booth algorithm produces the Booth encoded products with a value of zero when input data stream have sequentially equal values. Therefore, partial products have greater chances of being zero when the one with a smaller dynamic range of two inputs is used as a multiplier. To minimize greater switching activities of partial products, we propose a novel multiplication algorithm and its associated architecture. The proposed algorithm divides a multiplication expression into four multiplication expressions, and each multiplication is computed independently. Finally, the results of each multiplication are added. Therefore, the exchanging rate of two input data calculations can be higher during multiplication. Implementation results show the proposed multiplier can maximally save about 20% in terms of power dissipation than the previous Booth multiplier. |
doi_str_mv | 10.1109/APASIC.2004.1349403 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1349403</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1349403</ieee_id><sourcerecordid>1349403</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-829a4dbc30e165d903bf8197402096b873fc932639ec8206a3f49126e8ed4363</originalsourceid><addsrcrecordid>eNotj81Kw0AURgdEUGufoJt5gcQ7cyeTmY0Qgz-FgoJduCuT5MaOJJmQTC2-vYX22xw4iwMfYysBqRBgH4qP4nNdphJApQKVVYBX7A5yA2g05l83bDnPP3AaWsyEvGWPBe_CMRnDkSb-FELc8_7QRT92_iQOsx---RB-qeONi46Pboo--jDwnuI-NPfsunXdTMsLF2z78rwt35LN--u6LDaJF3kWEyOtU01VI5DQWWMBq9YImyuQYHVlcmxri1KjpdpI0A5bZYXUZKhRqHHBVuesJ6LdOPneTX-7y0P8B10pRlc</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A low-power Booth multiplier using novel data partition method</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Jongsu Park ; San Kim ; Yong-Surk Lee</creator><creatorcontrib>Jongsu Park ; San Kim ; Yong-Surk Lee</creatorcontrib><description>The Booth algorithm has a characteristic that the Booth algorithm produces the Booth encoded products with a value of zero when input data stream have sequentially equal values. Therefore, partial products have greater chances of being zero when the one with a smaller dynamic range of two inputs is used as a multiplier. To minimize greater switching activities of partial products, we propose a novel multiplication algorithm and its associated architecture. The proposed algorithm divides a multiplication expression into four multiplication expressions, and each multiplication is computed independently. Finally, the results of each multiplication are added. Therefore, the exchanging rate of two input data calculations can be higher during multiplication. Implementation results show the proposed multiplier can maximally save about 20% in terms of power dissipation than the previous Booth multiplier.</description><identifier>ISBN: 078038637X</identifier><identifier>ISBN: 9780780386372</identifier><identifier>DOI: 10.1109/APASIC.2004.1349403</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitors ; Circuits ; Data engineering ; Digital signal processing ; Energy consumption ; Equations ; Laboratories ; Mobile communication ; Partitioning algorithms ; Signal processing algorithms</subject><ispartof>Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 2004, p.54-57</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1349403$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,4036,4037,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1349403$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jongsu Park</creatorcontrib><creatorcontrib>San Kim</creatorcontrib><creatorcontrib>Yong-Surk Lee</creatorcontrib><title>A low-power Booth multiplier using novel data partition method</title><title>Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits</title><addtitle>APASIC</addtitle><description>The Booth algorithm has a characteristic that the Booth algorithm produces the Booth encoded products with a value of zero when input data stream have sequentially equal values. Therefore, partial products have greater chances of being zero when the one with a smaller dynamic range of two inputs is used as a multiplier. To minimize greater switching activities of partial products, we propose a novel multiplication algorithm and its associated architecture. The proposed algorithm divides a multiplication expression into four multiplication expressions, and each multiplication is computed independently. Finally, the results of each multiplication are added. Therefore, the exchanging rate of two input data calculations can be higher during multiplication. Implementation results show the proposed multiplier can maximally save about 20% in terms of power dissipation than the previous Booth multiplier.</description><subject>Capacitors</subject><subject>Circuits</subject><subject>Data engineering</subject><subject>Digital signal processing</subject><subject>Energy consumption</subject><subject>Equations</subject><subject>Laboratories</subject><subject>Mobile communication</subject><subject>Partitioning algorithms</subject><subject>Signal processing algorithms</subject><isbn>078038637X</isbn><isbn>9780780386372</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81Kw0AURgdEUGufoJt5gcQ7cyeTmY0Qgz-FgoJduCuT5MaOJJmQTC2-vYX22xw4iwMfYysBqRBgH4qP4nNdphJApQKVVYBX7A5yA2g05l83bDnPP3AaWsyEvGWPBe_CMRnDkSb-FELc8_7QRT92_iQOsx---RB-qeONi46Pboo--jDwnuI-NPfsunXdTMsLF2z78rwt35LN--u6LDaJF3kWEyOtU01VI5DQWWMBq9YImyuQYHVlcmxri1KjpdpI0A5bZYXUZKhRqHHBVuesJ6LdOPneTX-7y0P8B10pRlc</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Jongsu Park</creator><creator>San Kim</creator><creator>Yong-Surk Lee</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2004</creationdate><title>A low-power Booth multiplier using novel data partition method</title><author>Jongsu Park ; San Kim ; Yong-Surk Lee</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-829a4dbc30e165d903bf8197402096b873fc932639ec8206a3f49126e8ed4363</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Capacitors</topic><topic>Circuits</topic><topic>Data engineering</topic><topic>Digital signal processing</topic><topic>Energy consumption</topic><topic>Equations</topic><topic>Laboratories</topic><topic>Mobile communication</topic><topic>Partitioning algorithms</topic><topic>Signal processing algorithms</topic><toplevel>online_resources</toplevel><creatorcontrib>Jongsu Park</creatorcontrib><creatorcontrib>San Kim</creatorcontrib><creatorcontrib>Yong-Surk Lee</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jongsu Park</au><au>San Kim</au><au>Yong-Surk Lee</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A low-power Booth multiplier using novel data partition method</atitle><btitle>Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits</btitle><stitle>APASIC</stitle><date>2004</date><risdate>2004</risdate><spage>54</spage><epage>57</epage><pages>54-57</pages><isbn>078038637X</isbn><isbn>9780780386372</isbn><abstract>The Booth algorithm has a characteristic that the Booth algorithm produces the Booth encoded products with a value of zero when input data stream have sequentially equal values. Therefore, partial products have greater chances of being zero when the one with a smaller dynamic range of two inputs is used as a multiplier. To minimize greater switching activities of partial products, we propose a novel multiplication algorithm and its associated architecture. The proposed algorithm divides a multiplication expression into four multiplication expressions, and each multiplication is computed independently. Finally, the results of each multiplication are added. Therefore, the exchanging rate of two input data calculations can be higher during multiplication. Implementation results show the proposed multiplier can maximally save about 20% in terms of power dissipation than the previous Booth multiplier.</abstract><pub>IEEE</pub><doi>10.1109/APASIC.2004.1349403</doi><tpages>4</tpages></addata></record> |
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subjects | Capacitors Circuits Data engineering Digital signal processing Energy consumption Equations Laboratories Mobile communication Partitioning algorithms Signal processing algorithms |
title | A low-power Booth multiplier using novel data partition method |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T19%3A42%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20low-power%20Booth%20multiplier%20using%20novel%20data%20partition%20method&rft.btitle=Proceedings%20of%202004%20IEEE%20Asia-Pacific%20Conference%20on%20Advanced%20System%20Integrated%20Circuits&rft.au=Jongsu%20Park&rft.date=2004&rft.spage=54&rft.epage=57&rft.pages=54-57&rft.isbn=078038637X&rft.isbn_list=9780780386372&rft_id=info:doi/10.1109/APASIC.2004.1349403&rft_dat=%3Cieee_6IE%3E1349403%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1349403&rfr_iscdi=true |