PLUS: a distributed shared-memory system
PLUS is a multiprocessor architecture tailored to the fast execution of a single multithreaded process; its goal is to accelerate the execution of CPU-bound applications. PLUS supports shared memory and efficient synchronization. Memory access latency is reduced by nondemand replication of pages wit...
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creator | Bisiani, R. Ravishankar, M. |
description | PLUS is a multiprocessor architecture tailored to the fast execution of a single multithreaded process; its goal is to accelerate the execution of CPU-bound applications. PLUS supports shared memory and efficient synchronization. Memory access latency is reduced by nondemand replication of pages with hardware-supported coherence between replicated pages. The architecture has been simulated in detail, and some of the key measurements that have been used to substantiate the architectural decisions are presented. The current implementation of PLUS is also described.< > |
doi_str_mv | 10.1109/ISCA.1990.134514 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_134514</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>134514</ieee_id><sourcerecordid>134514</sourcerecordid><originalsourceid>FETCH-LOGICAL-i172t-713268e1d461c96fe56ad56b24e2c088448a441a91a1811fa30b0c7b430d44aa3</originalsourceid><addsrcrecordid>eNotj01Lw0AURQdEUGr24ipLN6nzZt58uStBbSGgULsuL5kXHDEoM3GRf2-h3s3hbA5cIW5BrgFkeNjt280aQjipRgN4IargvPTgrZLo_JWoSvmUpxnjpYVrcf_WHfaPNdUxlTmn_nfmWJcPyhybiafvvNRlKTNPN-JypK_C1T9X4vD89N5um-71ZdduuiaBU3PjQCvrGSJaGIId2ViKxvYKWQ3Se0RPiEABCDzASFr2cnA9ahkRifRK3J27iZmPPzlNlJfj-Y7-AwA5Pdw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>PLUS: a distributed shared-memory system</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Bisiani, R. ; Ravishankar, M.</creator><creatorcontrib>Bisiani, R. ; Ravishankar, M.</creatorcontrib><description>PLUS is a multiprocessor architecture tailored to the fast execution of a single multithreaded process; its goal is to accelerate the execution of CPU-bound applications. PLUS supports shared memory and efficient synchronization. Memory access latency is reduced by nondemand replication of pages with hardware-supported coherence between replicated pages. The architecture has been simulated in detail, and some of the key measurements that have been used to substantiate the architectural decisions are presented. The current implementation of PLUS is also described.< ></description><identifier>ISBN: 9780818620478</identifier><identifier>ISBN: 0818620471</identifier><identifier>DOI: 10.1109/ISCA.1990.134514</identifier><language>eng</language><publisher>IEEE Comput. Soc. Press</publisher><subject>Acceleration ; Access protocols ; Application software ; Coherence ; Computer architecture ; Computer science ; Delay ; Hardware ; Parallel processing ; Programming profession</subject><ispartof>[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture, 1990, p.115-124</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/134514$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/134514$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bisiani, R.</creatorcontrib><creatorcontrib>Ravishankar, M.</creatorcontrib><title>PLUS: a distributed shared-memory system</title><title>[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture</title><addtitle>ISCA</addtitle><description>PLUS is a multiprocessor architecture tailored to the fast execution of a single multithreaded process; its goal is to accelerate the execution of CPU-bound applications. PLUS supports shared memory and efficient synchronization. Memory access latency is reduced by nondemand replication of pages with hardware-supported coherence between replicated pages. The architecture has been simulated in detail, and some of the key measurements that have been used to substantiate the architectural decisions are presented. The current implementation of PLUS is also described.< ></description><subject>Acceleration</subject><subject>Access protocols</subject><subject>Application software</subject><subject>Coherence</subject><subject>Computer architecture</subject><subject>Computer science</subject><subject>Delay</subject><subject>Hardware</subject><subject>Parallel processing</subject><subject>Programming profession</subject><isbn>9780818620478</isbn><isbn>0818620471</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1990</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj01Lw0AURQdEUGr24ipLN6nzZt58uStBbSGgULsuL5kXHDEoM3GRf2-h3s3hbA5cIW5BrgFkeNjt280aQjipRgN4IargvPTgrZLo_JWoSvmUpxnjpYVrcf_WHfaPNdUxlTmn_nfmWJcPyhybiafvvNRlKTNPN-JypK_C1T9X4vD89N5um-71ZdduuiaBU3PjQCvrGSJaGIId2ViKxvYKWQ3Se0RPiEABCDzASFr2cnA9ahkRifRK3J27iZmPPzlNlJfj-Y7-AwA5Pdw</recordid><startdate>1990</startdate><enddate>1990</enddate><creator>Bisiani, R.</creator><creator>Ravishankar, M.</creator><general>IEEE Comput. Soc. Press</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1990</creationdate><title>PLUS: a distributed shared-memory system</title><author>Bisiani, R. ; Ravishankar, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-713268e1d461c96fe56ad56b24e2c088448a441a91a1811fa30b0c7b430d44aa3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1990</creationdate><topic>Acceleration</topic><topic>Access protocols</topic><topic>Application software</topic><topic>Coherence</topic><topic>Computer architecture</topic><topic>Computer science</topic><topic>Delay</topic><topic>Hardware</topic><topic>Parallel processing</topic><topic>Programming profession</topic><toplevel>online_resources</toplevel><creatorcontrib>Bisiani, R.</creatorcontrib><creatorcontrib>Ravishankar, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bisiani, R.</au><au>Ravishankar, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>PLUS: a distributed shared-memory system</atitle><btitle>[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture</btitle><stitle>ISCA</stitle><date>1990</date><risdate>1990</risdate><spage>115</spage><epage>124</epage><pages>115-124</pages><isbn>9780818620478</isbn><isbn>0818620471</isbn><abstract>PLUS is a multiprocessor architecture tailored to the fast execution of a single multithreaded process; its goal is to accelerate the execution of CPU-bound applications. PLUS supports shared memory and efficient synchronization. Memory access latency is reduced by nondemand replication of pages with hardware-supported coherence between replicated pages. The architecture has been simulated in detail, and some of the key measurements that have been used to substantiate the architectural decisions are presented. The current implementation of PLUS is also described.< ></abstract><pub>IEEE Comput. Soc. Press</pub><doi>10.1109/ISCA.1990.134514</doi><tpages>10</tpages></addata></record> |
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subjects | Acceleration Access protocols Application software Coherence Computer architecture Computer science Delay Hardware Parallel processing Programming profession |
title | PLUS: a distributed shared-memory system |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T17%3A58%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=PLUS:%20a%20distributed%20shared-memory%20system&rft.btitle=%5B1990%5D%20Proceedings.%20The%2017th%20Annual%20International%20Symposium%20on%20Computer%20Architecture&rft.au=Bisiani,%20R.&rft.date=1990&rft.spage=115&rft.epage=124&rft.pages=115-124&rft.isbn=9780818620478&rft.isbn_list=0818620471&rft_id=info:doi/10.1109/ISCA.1990.134514&rft_dat=%3Cieee_6IE%3E134514%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=134514&rfr_iscdi=true |