A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits non-return-to-zero signaling are developed. Test chips stacked at a distance of 300/spl mu/m communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35/s...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Mizoguchi, D., Yusof, Y.B., Miura, N., Sakura, T., Kuroda, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied sciences
Coupling circuits
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Inductors
Integrated circuit interconnections
Integrated circuits
Low pass filters
Magnetic analysis
Packaging
Protection
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Three-dimensional integrated circuits
Transmitters
Voltage
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Beschreibung
Zusammenfassung:A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits non-return-to-zero signaling are developed. Test chips stacked at a distance of 300/spl mu/m communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35/spl mu/m CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2004.1332634