Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit
A multi-valued logic (MVL) pass gate is an important element in configuring multi-valued logic. Multiple logical levels, which are different from binary pass gates, are required to be discriminated in MVL pass gates. In this paper, we designed the quaternary MIN (QMIN)/negated MIN (QNMIN) gate, and...
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| creator | Soo Jin Park Byoung Hee Yoon Kwang Sub Yoon Heung Soo Kim |
| description | A multi-valued logic (MVL) pass gate is an important element in configuring multi-valued logic. Multiple logical levels, which are different from binary pass gates, are required to be discriminated in MVL pass gates. In this paper, we designed the quaternary MIN (QMIN)/negated MIN (QNMIN) gate, and the quaternary MAX (QMAX)/negated MAX (QNMAX) gate using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gates. In addition, we designed quaternary truncated sum (QTS) and quaternary truncated difference (QTD) gates using vMOS down literal circuits (DLC). The DPL improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates are composed of vMOS DLC. The proposed gates obtain the signal value, to realize various multi threshold voltage circuits. In this paper, these circuits use a 3 V power supply voltage and the parameters of the 0.35 /spl mu/m N-well 2-poly 4-metal CMOS technology. HSPICE simulation results are also presented. |
| doi_str_mv | 10.1109/ISMVL.2004.1319941 |
| format | Conference Proceeding |
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Multiple logical levels, which are different from binary pass gates, are required to be discriminated in MVL pass gates. In this paper, we designed the quaternary MIN (QMIN)/negated MIN (QNMIN) gate, and the quaternary MAX (QMAX)/negated MAX (QNMAX) gate using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gates. In addition, we designed quaternary truncated sum (QTS) and quaternary truncated difference (QTD) gates using vMOS down literal circuits (DLC). The DPL improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates are composed of vMOS DLC. The proposed gates obtain the signal value, to realize various multi threshold voltage circuits. In this paper, these circuits use a 3 V power supply voltage and the parameters of the 0.35 /spl mu/m N-well 2-poly 4-metal CMOS technology. HSPICE simulation results are also presented.</description><identifier>ISSN: 0195-623X</identifier><identifier>ISBN: 0769521304</identifier><identifier>ISBN: 9780769521305</identifier><identifier>EISSN: 2378-2226</identifier><identifier>DOI: 10.1109/ISMVL.2004.1319941</identifier><language>eng</language><publisher>Los Alamitos CA: IEEE</publisher><subject>Applied sciences ; Capacitance ; CMOS technology ; Computer science; control theory; systems ; Electronics ; Exact sciences and technology ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Logic circuits ; Logic design ; Logic gates ; Logical, boolean and switching functions ; Multivalued logic ; Neurons ; Page description languages ; Power supplies ; Semiconductor electronics. Microelectronics. Optoelectronics. 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Multiple logical levels, which are different from binary pass gates, are required to be discriminated in MVL pass gates. In this paper, we designed the quaternary MIN (QMIN)/negated MIN (QNMIN) gate, and the quaternary MAX (QMAX)/negated MAX (QNMAX) gate using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gates. In addition, we designed quaternary truncated sum (QTS) and quaternary truncated difference (QTD) gates using vMOS down literal circuits (DLC). The DPL improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates are composed of vMOS DLC. The proposed gates obtain the signal value, to realize various multi threshold voltage circuits. In this paper, these circuits use a 3 V power supply voltage and the parameters of the 0.35 /spl mu/m N-well 2-poly 4-metal CMOS technology. HSPICE simulation results are also presented.</description><subject>Applied sciences</subject><subject>Capacitance</subject><subject>CMOS technology</subject><subject>Computer science; control theory; systems</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Logic circuits</subject><subject>Logic design</subject><subject>Logic gates</subject><subject>Logical, boolean and switching functions</subject><subject>Multivalued logic</subject><subject>Neurons</subject><subject>Page description languages</subject><subject>Power supplies</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Theoretical computing</subject><subject>Threshold voltage</subject><issn>0195-623X</issn><issn>2378-2226</issn><isbn>0769521304</isbn><isbn>9780769521305</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkEtLw0AUhQcfYFv9A7qZjcvUO89kllJfhZQuquKuTJI7cSQmNZNQ_PcOtODqcrgfh3MOIdcM5oyBuVtuVu_5nAPIORPMGMlOyISLNEs45_qUTCHVRnEmQJ6RCTCjEs3FxwWZhvAFwIGnMCH1AwZft7Rz9Ge0A_at7X9p09W-pHXUdAy-rWnVjUWDdGdDSIbetsGHoeuP3N4Pn7TFse9aulpvIrxvaeOjmW1o6fty9MMlOXe2CXh1vDPy9vT4unhJ8vXzcnGfJ56DGBLHhVImBYFoGdOAViKWqbYmk1wWBp1QTCJwpjQUNlOiqEpbicJVApA5MSO3B98YtbSNi1lLH7a73n_HYluWKi3TTEfu5sB5RPx_H4YUf8IhZvI</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Soo Jin Park</creator><creator>Byoung Hee Yoon</creator><creator>Kwang Sub Yoon</creator><creator>Heung Soo Kim</creator><general>IEEE</general><general>IEEE Computer Society</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>IQODW</scope></search><sort><creationdate>2004</creationdate><title>Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit</title><author>Soo Jin Park ; Byoung Hee Yoon ; Kwang Sub Yoon ; Heung Soo Kim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i203t-f23559703eea1160ea4eec76a98424b9ef3514e021560ba853bdcad3bfd30e1f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Applied sciences</topic><topic>Capacitance</topic><topic>CMOS technology</topic><topic>Computer science; control theory; systems</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Logic circuits</topic><topic>Logic design</topic><topic>Logic gates</topic><topic>Logical, boolean and switching functions</topic><topic>Multivalued logic</topic><topic>Neurons</topic><topic>Page description languages</topic><topic>Power supplies</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Theoretical computing</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Soo Jin Park</creatorcontrib><creatorcontrib>Byoung Hee Yoon</creatorcontrib><creatorcontrib>Kwang Sub Yoon</creatorcontrib><creatorcontrib>Heung Soo Kim</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Soo Jin Park</au><au>Byoung Hee Yoon</au><au>Kwang Sub Yoon</au><au>Heung Soo Kim</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit</atitle><btitle>Proceedings. 34th International Symposium on Multiple-Valued Logic</btitle><stitle>ISMVL</stitle><date>2004</date><risdate>2004</risdate><spage>198</spage><epage>203</epage><pages>198-203</pages><issn>0195-623X</issn><eissn>2378-2226</eissn><isbn>0769521304</isbn><isbn>9780769521305</isbn><abstract>A multi-valued logic (MVL) pass gate is an important element in configuring multi-valued logic. Multiple logical levels, which are different from binary pass gates, are required to be discriminated in MVL pass gates. In this paper, we designed the quaternary MIN (QMIN)/negated MIN (QNMIN) gate, and the quaternary MAX (QMAX)/negated MAX (QNMAX) gate using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gates. In addition, we designed quaternary truncated sum (QTS) and quaternary truncated difference (QTD) gates using vMOS down literal circuits (DLC). The DPL improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates are composed of vMOS DLC. The proposed gates obtain the signal value, to realize various multi threshold voltage circuits. In this paper, these circuits use a 3 V power supply voltage and the parameters of the 0.35 /spl mu/m N-well 2-poly 4-metal CMOS technology. HSPICE simulation results are also presented.</abstract><cop>Los Alamitos CA</cop><pub>IEEE</pub><doi>10.1109/ISMVL.2004.1319941</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 0195-623X |
| ispartof | Proceedings. 34th International Symposium on Multiple-Valued Logic, 2004, p.198-203 |
| issn | 0195-623X 2378-2226 |
| language | eng |
| recordid | cdi_ieee_primary_1319941 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Applied sciences Capacitance CMOS technology Computer science control theory systems Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Logic circuits Logic design Logic gates Logical, boolean and switching functions Multivalued logic Neurons Page description languages Power supplies Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Theoretical computing Threshold voltage |
| title | Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit |
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