Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit

A multi-valued logic (MVL) pass gate is an important element in configuring multi-valued logic. Multiple logical levels, which are different from binary pass gates, are required to be discriminated in MVL pass gates. In this paper, we designed the quaternary MIN (QMIN)/negated MIN (QNMIN) gate, and the quaternary MAX (QMAX)/negated MAX (QNMAX) gate using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gates. In addition, we designed quaternary truncated sum (QTS) and quaternary truncated difference (QTD) gates using vMOS down literal circuits (DLC). The DPL improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates are composed of vMOS DLC. The proposed gates obtain the signal value, to realize various multi threshold voltage circuits. In this paper, these circuits use a 3 V power supply voltage and the parameters of the 0.35 /spl mu/m N-well 2-poly 4-metal CMOS technology. HSPICE simulation results are also presented.