Microarchitecture optimizations for exploiting memory-level parallelism

The performance of memory-bound commercial applications such as databases is limited by increasing memory latencies. In this paper, we show that exploiting memory-level parallelism (MLP) is an effective approach for improving the performance of these applications and that microarchitecture has a pro...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yuan Chou, Fahs, B., Abraham, S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application software Delay Frequency Microarchitecture Microprocessors Out of order Parallel processing Pipeline processing Prefetching
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