A method to diagnose faults in analog integrated circuits using artificial neural networks with pseudorandom noise as stimulus
This paper describes a new, fast and economical strategy for fault diagnosis of analog integrated circuits. The methodology is based on a technique of using a pseudo random noise generator as the test pattern generator and a model-based observer, which is implemented through a feed forward artificia...
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| creator | Barua, L. Kabisatpathy, P. Sinha, S. |
| description | This paper describes a new, fast and economical strategy for fault diagnosis of analog integrated circuits. The methodology is based on a technique of using a pseudo random noise generator as the test pattern generator and a model-based observer, which is implemented through a feed forward artificial neural network in the form of a single hidden-layer perceptron. The proposed methodology can be implemented in any personal computer with a data acquisition card for on-line operation. Its main advantages are the low time requirement for learning and diagnosing. The method is quite robust and is able to detect small component variations without problems. This technique has been successfully applied to diagnose both hard and soft faults in a bipolar junction transistor based operational amplifier and a MOS operational amplifier. |
| doi_str_mv | 10.1109/ICECS.2003.1302050 |
| format | Conference Proceeding |
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The methodology is based on a technique of using a pseudo random noise generator as the test pattern generator and a model-based observer, which is implemented through a feed forward artificial neural network in the form of a single hidden-layer perceptron. The proposed methodology can be implemented in any personal computer with a data acquisition card for on-line operation. Its main advantages are the low time requirement for learning and diagnosing. The method is quite robust and is able to detect small component variations without problems. This technique has been successfully applied to diagnose both hard and soft faults in a bipolar junction transistor based operational amplifier and a MOS operational amplifier.</description><identifier>ISBN: 0780381637</identifier><identifier>ISBN: 9780780381636</identifier><identifier>DOI: 10.1109/ICECS.2003.1302050</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analog integrated circuits ; Artificial neural networks ; Circuit faults ; Fault diagnosis ; Feeds ; Integrated circuit noise ; Microcomputers ; Noise generators ; Operational amplifiers ; Test pattern generators</subject><ispartof>10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. 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This technique has been successfully applied to diagnose both hard and soft faults in a bipolar junction transistor based operational amplifier and a MOS operational amplifier.</description><subject>Analog integrated circuits</subject><subject>Artificial neural networks</subject><subject>Circuit faults</subject><subject>Fault diagnosis</subject><subject>Feeds</subject><subject>Integrated circuit noise</subject><subject>Microcomputers</subject><subject>Noise generators</subject><subject>Operational amplifiers</subject><subject>Test pattern generators</subject><isbn>0780381637</isbn><isbn>9780780381636</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkEtLw0AUhQdE8NU_oJv5A613MnlMliVULRRcqOtyk7mTjiaZMg-KG3-7QXs234ED3-Iwdi9gJQTUj9tm07ytMgC5EhIyKOCC3UClQCpRyuqKLUL4hDmyzstSXbOfNR8pHpzm0XFtsZ9cIG4wDTFwO3GccHD93CL1HiNp3lnfJTuvKdip5-ijNbazOPCJkv9DPDn_FfjJxgM_BkraeZy0G_nk7GzHwEO0YxpSuGOXBodAizNv2cfT5r15We5en7fNere0oirispKmykyrSGWdabU2BYAQVKtcaWzzigh0S7nOoa2zQpZKCawJDXaQY9dl8pY9_HstEe2P3o7ov_fni-QvgvFhAQ</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Barua, L.</creator><creator>Kabisatpathy, P.</creator><creator>Sinha, S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2003</creationdate><title>A method to diagnose faults in analog integrated circuits using artificial neural networks with pseudorandom noise as stimulus</title><author>Barua, L. ; Kabisatpathy, P. ; Sinha, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-73f72fb8e82cfbddf50011e9848dab47ee0dbe4d40b92536881a9eafac04acc23</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Analog integrated circuits</topic><topic>Artificial neural networks</topic><topic>Circuit faults</topic><topic>Fault diagnosis</topic><topic>Feeds</topic><topic>Integrated circuit noise</topic><topic>Microcomputers</topic><topic>Noise generators</topic><topic>Operational amplifiers</topic><topic>Test pattern generators</topic><toplevel>online_resources</toplevel><creatorcontrib>Barua, L.</creatorcontrib><creatorcontrib>Kabisatpathy, P.</creatorcontrib><creatorcontrib>Sinha, S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Barua, L.</au><au>Kabisatpathy, P.</au><au>Sinha, S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A method to diagnose faults in analog integrated circuits using artificial neural networks with pseudorandom noise as stimulus</atitle><btitle>10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003</btitle><stitle>ICECS</stitle><date>2003</date><risdate>2003</risdate><volume>1</volume><spage>356</spage><epage>359 Vol.1</epage><pages>356-359 Vol.1</pages><isbn>0780381637</isbn><isbn>9780780381636</isbn><abstract>This paper describes a new, fast and economical strategy for fault diagnosis of analog integrated circuits. The methodology is based on a technique of using a pseudo random noise generator as the test pattern generator and a model-based observer, which is implemented through a feed forward artificial neural network in the form of a single hidden-layer perceptron. The proposed methodology can be implemented in any personal computer with a data acquisition card for on-line operation. Its main advantages are the low time requirement for learning and diagnosing. The method is quite robust and is able to detect small component variations without problems. This technique has been successfully applied to diagnose both hard and soft faults in a bipolar junction transistor based operational amplifier and a MOS operational amplifier.</abstract><pub>IEEE</pub><doi>10.1109/ICECS.2003.1302050</doi></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analog integrated circuits Artificial neural networks Circuit faults Fault diagnosis Feeds Integrated circuit noise Microcomputers Noise generators Operational amplifiers Test pattern generators |
| title | A method to diagnose faults in analog integrated circuits using artificial neural networks with pseudorandom noise as stimulus |
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