An FPGA implementation of 3D affine transformations
3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, Computer Aided Design (CAD) or visualization applications. This paper investigates the suitability of Field Programmable Gate Array (FPGA) devices...
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creator | Bensaali, F. Amira, A. Uzun, I.S. Ahmedsaid, A. |
description | 3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, Computer Aided Design (CAD) or visualization applications. This paper investigates the suitability of Field Programmable Gate Array (FPGA) devices as a low cost solution for implementing 3D affine trans formations. A proposed solution based on processing large matrix multiplication has been implemented, for large 3D models, on the RC1000-PP Celoxica board based development platform using Handel-C, a C-like language supporting parallelism, flexible data size and compilation of high-level programs directly into FPGA hardware. |
doi_str_mv | 10.1109/ICECS.2003.1301885 |
format | Conference Proceeding |
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Almost all PC systems now include 3D graphics accelerators for games, Computer Aided Design (CAD) or visualization applications. This paper investigates the suitability of Field Programmable Gate Array (FPGA) devices as a low cost solution for implementing 3D affine trans formations. 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ICECS 2003. Proceedings of the 2003</btitle><stitle>ICECS</stitle><date>2003</date><risdate>2003</risdate><volume>2</volume><spage>715</spage><epage>718 Vol.2</epage><pages>715-718 Vol.2</pages><isbn>0780381637</isbn><isbn>9780780381636</isbn><abstract>3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, Computer Aided Design (CAD) or visualization applications. This paper investigates the suitability of Field Programmable Gate Array (FPGA) devices as a low cost solution for implementing 3D affine trans formations. A proposed solution based on processing large matrix multiplication has been implemented, for large 3D models, on the RC1000-PP Celoxica board based development platform using Handel-C, a C-like language supporting parallelism, flexible data size and compilation of high-level programs directly into FPGA hardware.</abstract><pub>IEEE</pub><doi>10.1109/ICECS.2003.1301885</doi></addata></record> |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Acceleration Application software Computer applications Computer graphics Computer science Costs Design automation Field programmable gate arrays Hardware design languages Parallel processing |
title | An FPGA implementation of 3D affine transformations |
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