Parallelization of loops with exits on pipelined architectures

Modulo scheduling theory can be applied successfully to overlap Fortran DO loops on pipelined computers issuing multiple operations per cycle both with and without special loop architectural support. It is shown that a broader class of loops-repeat-until, while, and loops with more than one exit-whe...

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Bibliographische Detailangaben

Hauptverfasser:	Tirumalai, P., Lee, M., Schlansker, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Acceleration Computer architecture Hardware Laboratories Milling machines Parallel processing Pipeline processing Processor scheduling Prototypes VLIW
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