Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

Hardware implementations of the advanced encryption standard (AES) Rijndael algorithm have recently been the object of an intensive evaluation. Several papers describe efficient architectures for ASICs and FPGAs. In this context, the highest effort was devoted to high throughput (up to 20 Gbps) encr...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Rouvroy, G., Standaert, F.-X., Quisquater, J.-J., Legat, J.-D.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application specific integrated circuits Computer architecture Costs Cryptography Field programmable gate arrays Hardware Iterative algorithms NIST Protection Throughput
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!