Evaluation of network topologies for a run time re-routable network on a programmable chip

Networks on a chip have become a popular way to integrate IP cores. In the field programmable logic domain there is the added possibility that IP cores can be added and removed from the chip using run time reconfiguration. The widely advocated fixed mesh packet forwarding network topology, where the...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kearney, D.A., Veldman, G.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer network management Computer networks Field programmable gate arrays Network topology Network-on-a-chip Programmable logic arrays Programmable logic devices Prototypes Routing Tiles
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