Mappability estimate: a measure of the goodness of a processor-algorithm pair
A quick way of measuring the goodness of a processor-algorithm pair is presented. The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture character...
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description | A quick way of measuring the goodness of a processor-algorithm pair is presented. The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture characteristics are considered. The mappability estimation approach is demonstrated using MiBench benchmark algorithms and the Simplescalar processor simulator with ARM instruction set. The estimation results are consistent with the simulations and the estimates correctly predicted the most suitable architectures for three of the four algorithms. |
doi_str_mv | 10.1109/ISSOC.2003.1267731 |
format | Conference Proceeding |
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The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture characteristics are considered. The mappability estimation approach is demonstrated using MiBench benchmark algorithms and the Simplescalar processor simulator with ARM instruction set. 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The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture characteristics are considered. The mappability estimation approach is demonstrated using MiBench benchmark algorithms and the Simplescalar processor simulator with ARM instruction set. The estimation results are consistent with the simulations and the estimates correctly predicted the most suitable architectures for three of the four algorithms.</description><subject>Clocks</subject><subject>Computational modeling</subject><subject>Computer architecture</subject><subject>Computer networks</subject><subject>Costs</subject><subject>Information analysis</subject><subject>Predictive models</subject><subject>Resource management</subject><subject>Silicon</subject><subject>Usability</subject><isbn>0780381602</isbn><isbn>9780780381605</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tOwzAURC0hJKD0B2DjH0i4tmM7ZociHpVadVFYVzfhujVKcGSHRf-eIDqb0dkczTB2J6AUAtzDarfbNqUEUKWQxlolLtgN2BpULQzIK7bM-QvmVLrSEq7ZZoPjiG3ow3TilKcw4ESPHPlAmH8S8ej5dCR-iPHzm3L-Y-Rjit0MMRXYH2IK03HgI4Z0yy499pmW516wj5fn9-atWG9fV83TugjC6qkg6EDUUqGySLYVnfMesa6M9K0TrjZgSRtJwiFq7NC0lRVQkbfSkdSgFuz-3xuIaD-meXU67c-P1S-fxEyn</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Kreku, J.</creator><creator>Soininen, J.-P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2003</creationdate><title>Mappability estimate: a measure of the goodness of a processor-algorithm pair</title><author>Kreku, J. ; Soininen, J.-P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-e0c01823a37ae7b1c9ffaa8462fb9198607e562e19aa5aca6b47104ef729e2503</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Clocks</topic><topic>Computational modeling</topic><topic>Computer architecture</topic><topic>Computer networks</topic><topic>Costs</topic><topic>Information analysis</topic><topic>Predictive models</topic><topic>Resource management</topic><topic>Silicon</topic><topic>Usability</topic><toplevel>online_resources</toplevel><creatorcontrib>Kreku, J.</creatorcontrib><creatorcontrib>Soininen, J.-P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kreku, J.</au><au>Soininen, J.-P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Mappability estimate: a measure of the goodness of a processor-algorithm pair</atitle><btitle>Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)</btitle><stitle>ISSOC</stitle><date>2003</date><risdate>2003</risdate><spage>119</spage><epage>122</epage><pages>119-122</pages><isbn>0780381602</isbn><isbn>9780780381605</isbn><abstract>A quick way of measuring the goodness of a processor-algorithm pair is presented. The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture characteristics are considered. The mappability estimation approach is demonstrated using MiBench benchmark algorithms and the Simplescalar processor simulator with ARM instruction set. The estimation results are consistent with the simulations and the estimates correctly predicted the most suitable architectures for three of the four algorithms.</abstract><pub>IEEE</pub><doi>10.1109/ISSOC.2003.1267731</doi><tpages>4</tpages></addata></record> |
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subjects | Clocks Computational modeling Computer architecture Computer networks Costs Information analysis Predictive models Resource management Silicon Usability |
title | Mappability estimate: a measure of the goodness of a processor-algorithm pair |
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