A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback
This paper presents a previously unpublished technique for the reduction of the sensitivity to clock jitter in continuous-time sigma-delta modulators. Therefore, the main clock jitter source, the feedback digital-to-analog converter, is implemented by using a sloping feedback pulse-form, which is ge...
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| creator | Ortmanns, M. Gerfers, F. Manoli, Y. |
| description | This paper presents a previously unpublished technique for the reduction of the sensitivity to clock jitter in continuous-time sigma-delta modulators. Therefore, the main clock jitter source, the feedback digital-to-analog converter, is implemented by using a sloping feedback pulse-form, which is generated by a transistor current source and a circuit to generate the slope. In this first implementation, a third-order continuous-time modulator has been designed, achieving 10 bits of resolution and consuming only 250/spl mu/W from a 1.5V supply, while the jitter sensitivity could be remarkably reduced. |
| doi_str_mv | 10.1109/ESSCIRC.2003.1257119 |
| format | Conference Proceeding |
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Therefore, the main clock jitter source, the feedback digital-to-analog converter, is implemented by using a sloping feedback pulse-form, which is generated by a transistor current source and a circuit to generate the slope. In this first implementation, a third-order continuous-time modulator has been designed, achieving 10 bits of resolution and consuming only 250/spl mu/W from a 1.5V supply, while the jitter sensitivity could be remarkably reduced.</description><identifier>ISBN: 0780379950</identifier><identifier>ISBN: 9780780379954</identifier><identifier>DOI: 10.1109/ESSCIRC.2003.1257119</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitors ; Clocks ; Delta-sigma modulation ; Feedback circuits ; Jitter ; Pulse circuits ; Pulse generation ; Resistors ; Sampling methods ; Thyristors</subject><ispartof>ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. 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No.03EX705)</title><addtitle>ESSCIR</addtitle><description>This paper presents a previously unpublished technique for the reduction of the sensitivity to clock jitter in continuous-time sigma-delta modulators. Therefore, the main clock jitter source, the feedback digital-to-analog converter, is implemented by using a sloping feedback pulse-form, which is generated by a transistor current source and a circuit to generate the slope. In this first implementation, a third-order continuous-time modulator has been designed, achieving 10 bits of resolution and consuming only 250/spl mu/W from a 1.5V supply, while the jitter sensitivity could be remarkably reduced.</description><subject>Capacitors</subject><subject>Clocks</subject><subject>Delta-sigma modulation</subject><subject>Feedback circuits</subject><subject>Jitter</subject><subject>Pulse circuits</subject><subject>Pulse generation</subject><subject>Resistors</subject><subject>Sampling methods</subject><subject>Thyristors</subject><isbn>0780379950</isbn><isbn>9780780379954</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkN1KAzEUhAMiqLVPoBd5ga3Jno3ZXJalaqEgWL2uJ9mzNro_Jckivr1d2rmYgQ9mLoaxeykWUgrzsNpuq_VbtciFgIXMlZbSXLAboUsB2hglrtg8xm9xFJhHZeCafS65G_rk-3EYY5Z8Rzz6rw6zmtqEvBvqscU0BP7r057Ho7s91dzhAZ2f-NQOQ9tOcAyB-jSViDdEtUX3c8suG2wjzc85Yx9Pq_fqJdu8Pq-r5SbzUquUFYXVEnIhtQZC0NZgUTYiB9eAVYUypQMNItfKWjTSOsC6dqgbU5JBjTBjd6ddT0S7Q_Adhr_d-QT4B8A_VTQ</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Ortmanns, M.</creator><creator>Gerfers, F.</creator><creator>Manoli, Y.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2003</creationdate><title>A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback</title><author>Ortmanns, M. ; Gerfers, F. ; Manoli, Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-44b713201773ea37b9a48f023cf3b54598c3730275bba91bc3addca7f98e9a7a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Capacitors</topic><topic>Clocks</topic><topic>Delta-sigma modulation</topic><topic>Feedback circuits</topic><topic>Jitter</topic><topic>Pulse circuits</topic><topic>Pulse generation</topic><topic>Resistors</topic><topic>Sampling methods</topic><topic>Thyristors</topic><toplevel>online_resources</toplevel><creatorcontrib>Ortmanns, M.</creatorcontrib><creatorcontrib>Gerfers, F.</creatorcontrib><creatorcontrib>Manoli, Y.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ortmanns, M.</au><au>Gerfers, F.</au><au>Manoli, Y.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback</atitle><btitle>ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705)</btitle><stitle>ESSCIR</stitle><date>2003</date><risdate>2003</risdate><spage>249</spage><epage>252</epage><pages>249-252</pages><isbn>0780379950</isbn><isbn>9780780379954</isbn><abstract>This paper presents a previously unpublished technique for the reduction of the sensitivity to clock jitter in continuous-time sigma-delta modulators. Therefore, the main clock jitter source, the feedback digital-to-analog converter, is implemented by using a sloping feedback pulse-form, which is generated by a transistor current source and a circuit to generate the slope. In this first implementation, a third-order continuous-time modulator has been designed, achieving 10 bits of resolution and consuming only 250/spl mu/W from a 1.5V supply, while the jitter sensitivity could be remarkably reduced.</abstract><pub>IEEE</pub><doi>10.1109/ESSCIRC.2003.1257119</doi><tpages>4</tpages></addata></record> |
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| ispartof | ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), 2003, p.249-252 |
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| language | eng |
| recordid | cdi_ieee_primary_1257119 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitors Clocks Delta-sigma modulation Feedback circuits Jitter Pulse circuits Pulse generation Resistors Sampling methods Thyristors |
| title | A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback |
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