Failure of multiple-cell power DMOS transistors in avalanche operation

We continued the work presented in (A. Icaza Deckelmann et al., Proc. of the 32nd Europ. Solid State Res. Conf. (ESSDERC), p.459-462, 2002), showing by multiple-cell device simulation that the failure mechanism found for a single DMOS transistor cell, indeed applies to a multiple-cell array, when the simplified model is extended to the whole device structure. Moreover, the current crowding phenomenon predicted by the model in the previous work is corroborated by experimental failure analysis. Current filamentation, which had already been indicated by 2D-simulation could now be demonstrated by means of 3D-simulation. In this context, it showed that a physically rigorous electrothermal transport model is mandatory in order to achieve a good agreement with experimental data.