Error detection in signed digit arithmetic circuit with parity checker [adder example]

This paper proposes a methodology for the development of simple arithmetic self-checking circuits using a signed digit representation. In particular, the architecture of an adder is reported and its self-checking capability with respect to the stuck-at fault set is shown. The main idea underlying th...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Cardarilli, G.C., Ottavi, M., Pontarelli, S., Re, M., Salsano, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Adders Application specific integrated circuits Arithmetic Circuit faults Computer applications Computer architecture Electrical fault detection Fault detection Integrated circuit reliability Pervasive computing
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