BiST model for IC RF-transceiver front-end
In this paper, a BiST technique for an RF transceiver front-end is presented. The test is aimed at spot defects typical of mass production in the CMOS process. The loop-back approach is used to detect faults modeled as resistive breaks or bridges. The resulting impairment in gain, noise figure or se...
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| creator | Dabrowski, J. |
| description | In this paper, a BiST technique for an RF transceiver front-end is presented. The test is aimed at spot defects typical of mass production in the CMOS process. The loop-back approach is used to detect faults modeled as resistive breaks or bridges. The resulting impairment in gain, noise figure or selectivity of the RF blocks are considered functional-level faults, and as such are subjected to test with PRBS stimulus and BER as the response at base-band. The extra test circuitry is limited and the on-chip resources are used to set-up the BiST. A model of a GSM transceiver with BiST is investigated to verify the proposed approach. |
| doi_str_mv | 10.1109/DFTVS.2003.1250124 |
| format | Conference Proceeding |
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The test is aimed at spot defects typical of mass production in the CMOS process. The loop-back approach is used to detect faults modeled as resistive breaks or bridges. The resulting impairment in gain, noise figure or selectivity of the RF blocks are considered functional-level faults, and as such are subjected to test with PRBS stimulus and BER as the response at base-band. The extra test circuitry is limited and the on-chip resources are used to set-up the BiST. A model of a GSM transceiver with BiST is investigated to verify the proposed approach.</description><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>CMOS process</subject><subject>Electrical fault detection</subject><subject>Fault detection</subject><subject>Integrated circuit modeling</subject><subject>Mass production</subject><subject>Radio frequency</subject><subject>Semiconductor device modeling</subject><subject>Transceivers</subject><issn>1550-5774</issn><issn>2377-7966</issn><isbn>9780769520421</isbn><isbn>0769520421</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81Kw0AYRQd_wFDzArrJWpj0m_-ZpUajhULBRrdlMvkGIm0ikyD49gbs3dzFuRy4hNwxKBkDt36um899yQFEybgCxuUFybgwhhqn9SXJnbFgtFMcJGdXJGNKAVXGyBuST9MXLBFOOM0z8vDU75viNHZ4LOKYik1VvNd0Tn6YAvY_mIqYxmGmOHS35Dr644T5uVfko35pqje63b1uqsctDUzJmYYoeCsj2hZk28UOILRat14iD8FbD15Eg2iXGQ--i9Zw6ZgVILSzCxErcv_v7RHx8J36k0-_h_NT8Qc4FEQC</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Dabrowski, J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2003</creationdate><title>BiST model for IC RF-transceiver front-end</title><author>Dabrowski, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c154t-cf32b4fe8b04bdfd00cb66ba4e2cca8a0a3f7ee8f322cadf8724918303698f7e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>CMOS process</topic><topic>Electrical fault detection</topic><topic>Fault detection</topic><topic>Integrated circuit modeling</topic><topic>Mass production</topic><topic>Radio frequency</topic><topic>Semiconductor device modeling</topic><topic>Transceivers</topic><toplevel>online_resources</toplevel><creatorcontrib>Dabrowski, J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dabrowski, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>BiST model for IC RF-transceiver front-end</atitle><btitle>Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems</btitle><stitle>DFTVS</stitle><date>2003</date><risdate>2003</risdate><spage>295</spage><epage>302</epage><pages>295-302</pages><issn>1550-5774</issn><eissn>2377-7966</eissn><isbn>9780769520421</isbn><isbn>0769520421</isbn><abstract>In this paper, a BiST technique for an RF transceiver front-end is presented. The test is aimed at spot defects typical of mass production in the CMOS process. The loop-back approach is used to detect faults modeled as resistive breaks or bridges. The resulting impairment in gain, noise figure or selectivity of the RF blocks are considered functional-level faults, and as such are subjected to test with PRBS stimulus and BER as the response at base-band. The extra test circuitry is limited and the on-chip resources are used to set-up the BiST. A model of a GSM transceiver with BiST is investigated to verify the proposed approach.</abstract><pub>IEEE</pub><doi>10.1109/DFTVS.2003.1250124</doi><tpages>8</tpages></addata></record> |
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| identifier | ISSN: 1550-5774 |
| ispartof | Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, p.295-302 |
| issn | 1550-5774 2377-7966 |
| language | eng |
| recordid | cdi_ieee_primary_1250124 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit faults Circuit testing CMOS process Electrical fault detection Fault detection Integrated circuit modeling Mass production Radio frequency Semiconductor device modeling Transceivers |
| title | BiST model for IC RF-transceiver front-end |
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