Yield analysis of compiler-based arrays of embedded SRAMs

Yield analysis of compiler-based arrays of embedded SRAMs

This paper presents a detailed analysis of the yield of embedded static random access memories (eSRAM) which are generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into account the design constructs (referred to as kernels) and...

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Hauptverfasser: Wang, X., Ottavi, M., Lombardi, F.
Format: Tagungsbericht
Sprache:eng
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Application specific integrated circuits
Circuit faults
Driver circuits
Industrial relations
Integrated circuit yield
Kernel
Manufacturing industries
Monitoring
Random access memory
Redundancy
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Ottavi, M.
Lombardi, F.
description This paper presents a detailed analysis of the yield of embedded static random access memories (eSRAM) which are generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into account the design constructs (referred to as kernels) and the physical properties of the layout. The new tool CAYA (Compiler-based Array Yield Analysis) is based on a characterization of the design process which accounts for fault types and the relation between functional and structural faults; a novel empirical model is proposed to facilitate the yield calculation. Industrial data is provided for the analysis of various configurations with different structures and redundancy. The effectiveness and accuracy as provided by CAYA are assessed with respect to industrial designs.
doi_str_mv 10.1109/DFTVS.2003.1250089
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subjects Application specific integrated circuits
Circuit faults
Driver circuits
Industrial relations
Integrated circuit yield
Kernel
Manufacturing industries
Monitoring
Random access memory
Redundancy
title Yield analysis of compiler-based arrays of embedded SRAMs
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