Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters
Since advanced microprocessors are designed based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity...
Gespeichert in:
Hauptverfasser: | , , , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 332 |
---|---|
container_issue | |
container_start_page | 329 |
container_title | |
container_volume | |
creator | Kobrinsky, M.J. Chakravarty, S. Dan Jiao Harmes, M. List, S. Mazumder, M. |
description | Since advanced microprocessors are designed based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and fullwave simulation tools, for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the trade-offs between accuracy and computation expenses for a large variety of cases. |
doi_str_mv | 10.1109/EPEP.2003.1250061 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1250061</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1250061</ieee_id><sourcerecordid>1250061</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-16ed960c99b21560ea1273700ef4bff5f24642afe978996ef9353f3f4b6205ac3</originalsourceid><addsrcrecordid>eNotkN1KAzEQhQMiKHUfQLzJC2ydJJvs5lLK-gMFC-p1SdNJG93NbpOt6Nsbag8DB74ZBs4h5JbBnDHQ9-2qXc05gJgzLgEUuyCFrhvIIxrGG3lFipQ-IUvoSih-TQ7tz4jR9xgm09Fv0_mtmfwQ6OCojUNKGX_R5Ptjd-KJuiHSIZR270fqw4TRDiGgnRI1E9373Z66iIcjBusx0WPyYUffytFE02O-Tjfk0pkuYXH2Gfl4bN8Xz-Xy9ell8bAsPavlVDKFW63Aar3hTCpAw3gtagB01cY56XilKm4c5oBaK3RaSOFEXioO0lgxI3f_fz0irsec0cTf9bkY8QeSCltW</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Kobrinsky, M.J. ; Chakravarty, S. ; Dan Jiao ; Harmes, M. ; List, S. ; Mazumder, M.</creator><creatorcontrib>Kobrinsky, M.J. ; Chakravarty, S. ; Dan Jiao ; Harmes, M. ; List, S. ; Mazumder, M.</creatorcontrib><description>Since advanced microprocessors are designed based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and fullwave simulation tools, for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the trade-offs between accuracy and computation expenses for a large variety of cases.</description><identifier>ISBN: 9780780381285</identifier><identifier>ISBN: 0780381289</identifier><identifier>DOI: 10.1109/EPEP.2003.1250061</identifier><language>eng</language><publisher>IEEE</publisher><subject>Concurrent computing ; Conductors ; Crosstalk ; Electrical resistance measurement ; Frequency measurement ; Logic ; Noise measurement ; Scattering parameters ; Signal processing ; Testing</subject><ispartof>Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710), 2003, p.329-332</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1250061$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1250061$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kobrinsky, M.J.</creatorcontrib><creatorcontrib>Chakravarty, S.</creatorcontrib><creatorcontrib>Dan Jiao</creatorcontrib><creatorcontrib>Harmes, M.</creatorcontrib><creatorcontrib>List, S.</creatorcontrib><creatorcontrib>Mazumder, M.</creatorcontrib><title>Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters</title><title>Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)</title><addtitle>EPEP</addtitle><description>Since advanced microprocessors are designed based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and fullwave simulation tools, for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the trade-offs between accuracy and computation expenses for a large variety of cases.</description><subject>Concurrent computing</subject><subject>Conductors</subject><subject>Crosstalk</subject><subject>Electrical resistance measurement</subject><subject>Frequency measurement</subject><subject>Logic</subject><subject>Noise measurement</subject><subject>Scattering parameters</subject><subject>Signal processing</subject><subject>Testing</subject><isbn>9780780381285</isbn><isbn>0780381289</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkN1KAzEQhQMiKHUfQLzJC2ydJJvs5lLK-gMFC-p1SdNJG93NbpOt6Nsbag8DB74ZBs4h5JbBnDHQ9-2qXc05gJgzLgEUuyCFrhvIIxrGG3lFipQ-IUvoSih-TQ7tz4jR9xgm09Fv0_mtmfwQ6OCojUNKGX_R5Ptjd-KJuiHSIZR270fqw4TRDiGgnRI1E9373Z66iIcjBusx0WPyYUffytFE02O-Tjfk0pkuYXH2Gfl4bN8Xz-Xy9ell8bAsPavlVDKFW63Aar3hTCpAw3gtagB01cY56XilKm4c5oBaK3RaSOFEXioO0lgxI3f_fz0irsec0cTf9bkY8QeSCltW</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Kobrinsky, M.J.</creator><creator>Chakravarty, S.</creator><creator>Dan Jiao</creator><creator>Harmes, M.</creator><creator>List, S.</creator><creator>Mazumder, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2003</creationdate><title>Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters</title><author>Kobrinsky, M.J. ; Chakravarty, S. ; Dan Jiao ; Harmes, M. ; List, S. ; Mazumder, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-16ed960c99b21560ea1273700ef4bff5f24642afe978996ef9353f3f4b6205ac3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Concurrent computing</topic><topic>Conductors</topic><topic>Crosstalk</topic><topic>Electrical resistance measurement</topic><topic>Frequency measurement</topic><topic>Logic</topic><topic>Noise measurement</topic><topic>Scattering parameters</topic><topic>Signal processing</topic><topic>Testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Kobrinsky, M.J.</creatorcontrib><creatorcontrib>Chakravarty, S.</creatorcontrib><creatorcontrib>Dan Jiao</creatorcontrib><creatorcontrib>Harmes, M.</creatorcontrib><creatorcontrib>List, S.</creatorcontrib><creatorcontrib>Mazumder, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kobrinsky, M.J.</au><au>Chakravarty, S.</au><au>Dan Jiao</au><au>Harmes, M.</au><au>List, S.</au><au>Mazumder, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters</atitle><btitle>Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)</btitle><stitle>EPEP</stitle><date>2003</date><risdate>2003</risdate><spage>329</spage><epage>332</epage><pages>329-332</pages><isbn>9780780381285</isbn><isbn>0780381289</isbn><abstract>Since advanced microprocessors are designed based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and fullwave simulation tools, for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the trade-offs between accuracy and computation expenses for a large variety of cases.</abstract><pub>IEEE</pub><doi>10.1109/EPEP.2003.1250061</doi><tpages>4</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISBN: 9780780381285 |
ispartof | Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710), 2003, p.329-332 |
issn | |
language | eng |
recordid | cdi_ieee_primary_1250061 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Concurrent computing Conductors Crosstalk Electrical resistance measurement Frequency measurement Logic Noise measurement Scattering parameters Signal processing Testing |
title | Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T16%3A23%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Experimental%20validation%20of%20crosstalk%20simulations%20for%20on-chip%20interconnects%20at%20high%20frequencies%20using%20S-parameters&rft.btitle=Electrical%20Performance%20of%20Electrical%20Packaging%20(IEEE%20Cat.%20No.%2003TH8710)&rft.au=Kobrinsky,%20M.J.&rft.date=2003&rft.spage=329&rft.epage=332&rft.pages=329-332&rft.isbn=9780780381285&rft.isbn_list=0780381289&rft_id=info:doi/10.1109/EPEP.2003.1250061&rft_dat=%3Cieee_6IE%3E1250061%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1250061&rfr_iscdi=true |