A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18/spl mu/m CMOS technology

A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	van de Beek, R.C.H., Vaucher, C.S., Leenaerts, D.M.W., Pavlovic, N., Mistry, K., Klumperink, E.A.M., Nauta, B.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuits Clocks CMOS technology Frequency conversion Jitter Optical transmitters Phase detection Phase frequency detector Signal generators Space vector pulse width modulation
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