A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18/spl mu/m CMOS technology
A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at...
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| container_end_page | 486 vol.1 |
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| container_start_page | 178 |
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| creator | van de Beek, R.C.H. Vaucher, C.S. Leenaerts, D.M.W. Pavlovic, N. Mistry, K. Klumperink, E.A.M. Nauta, B. |
| description | A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations. |
| doi_str_mv | 10.1109/ISSCC.2003.1234256 |
| format | Conference Proceeding |
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The jitter and power dissipation are lower than that of previous CMOS implementations.</description><subject>Circuits</subject><subject>Clocks</subject><subject>CMOS technology</subject><subject>Frequency conversion</subject><subject>Jitter</subject><subject>Optical transmitters</subject><subject>Phase detection</subject><subject>Phase frequency detector</subject><subject>Signal generators</subject><subject>Space vector pulse width modulation</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>0780377079</isbn><isbn>9780780377073</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9js1qwkAURi9tBaP1BdrNfYFM7sw0M8lSgtUupNC4roQwrWMnP2RGRJ_eLFx3deA7fHAAXjgxzilPPsqyKJggkowL-SZS9QCRkFrFmSL1CDPSGUmtSedPEBHPZaxSSVOYeX8kojRXWQTfSxQsxdAhp_XmirXr6j9sTi7Y3lkz4Km1Ac82HJCYEL3Hr22JRxvC6GyL1TjzLPG9G09Jg8X2s8Rg6kPbue738gyTn8p5s7hzDq_vq12xia0xZt8PtqmGy_7eL_-3N8rYQsU</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>van de Beek, R.C.H.</creator><creator>Vaucher, C.S.</creator><creator>Leenaerts, D.M.W.</creator><creator>Pavlovic, N.</creator><creator>Mistry, K.</creator><creator>Klumperink, E.A.M.</creator><creator>Nauta, B.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2003</creationdate><title>A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18/spl mu/m CMOS technology</title><author>van de Beek, R.C.H. ; Vaucher, C.S. ; Leenaerts, D.M.W. ; Pavlovic, N. ; Mistry, K. ; Klumperink, E.A.M. ; Nauta, B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_12342563</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Circuits</topic><topic>Clocks</topic><topic>CMOS technology</topic><topic>Frequency conversion</topic><topic>Jitter</topic><topic>Optical transmitters</topic><topic>Phase detection</topic><topic>Phase frequency detector</topic><topic>Signal generators</topic><topic>Space vector pulse width modulation</topic><toplevel>online_resources</toplevel><creatorcontrib>van de Beek, R.C.H.</creatorcontrib><creatorcontrib>Vaucher, C.S.</creatorcontrib><creatorcontrib>Leenaerts, D.M.W.</creatorcontrib><creatorcontrib>Pavlovic, N.</creatorcontrib><creatorcontrib>Mistry, K.</creatorcontrib><creatorcontrib>Klumperink, E.A.M.</creatorcontrib><creatorcontrib>Nauta, B.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>van de Beek, R.C.H.</au><au>Vaucher, C.S.</au><au>Leenaerts, D.M.W.</au><au>Pavlovic, N.</au><au>Mistry, K.</au><au>Klumperink, E.A.M.</au><au>Nauta, B.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18/spl mu/m CMOS technology</atitle><btitle>2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC</btitle><stitle>ISSCC</stitle><date>2003</date><risdate>2003</risdate><spage>178</spage><epage>486 vol.1</epage><pages>178-486 vol.1</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>0780377079</isbn><isbn>9780780377073</isbn><abstract>A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.2003.1234256</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0193-6530 |
| ispartof | 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.178-486 vol.1 |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_1234256 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Clocks CMOS technology Frequency conversion Jitter Optical transmitters Phase detection Phase frequency detector Signal generators Space vector pulse width modulation |
| title | A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18/spl mu/m CMOS technology |
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