A new design technique of hybrid SET/CMOS static memory cells
The single electron transistor(SET)/CMOS-based static memory cell is proposed. The negative differential conductance(NDC) characteristics of SET block help to realize very compact circuits for implementing the static memory cell, compared with the memory cells in conventional technologies. The propo...
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| creator | Bong-Hoon Lee Yoon-Ha Jeong |
| description | The single electron transistor(SET)/CMOS-based static memory cell is proposed. The negative differential conductance(NDC) characteristics of SET block help to realize very compact circuits for implementing the static memory cell, compared with the memory cells in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks having the NDC. The peak-to-valley current ratio of the SET block is above 5 with C/sub G/=5.4C/sub T/(C/sub T/=0.1aF) at T=77K. A read and write operation of the proposed memory cell was validated with SET/CMOS hybrid simulation at T=77K. Even though the fabrication process which integrate MOSFET devices and SET block with NDC is not available, these results suggest that the proposed SET/CMOS static memory cell is suitable for a high density memory system with the low power consumption. |
| doi_str_mv | 10.1109/NANO.2003.1231002 |
| format | Conference Proceeding |
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The negative differential conductance(NDC) characteristics of SET block help to realize very compact circuits for implementing the static memory cell, compared with the memory cells in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks having the NDC. The peak-to-valley current ratio of the SET block is above 5 with C/sub G/=5.4C/sub T/(C/sub T/=0.1aF) at T=77K. A read and write operation of the proposed memory cell was validated with SET/CMOS hybrid simulation at T=77K. Even though the fabrication process which integrate MOSFET devices and SET block with NDC is not available, these results suggest that the proposed SET/CMOS static memory cell is suitable for a high density memory system with the low power consumption.</description><identifier>ISBN: 0780379764</identifier><identifier>ISBN: 9780780379763</identifier><identifier>DOI: 10.1109/NANO.2003.1231002</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS memory circuits ; CMOS technology ; Electrons ; Energy consumption ; Fabrication ; MOSFET circuits ; Nanoscale devices ; Read-write memory ; Tunneling ; Voltage</subject><ispartof>2003 Third IEEE Conference on Nanotechnology, 2003. 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The negative differential conductance(NDC) characteristics of SET block help to realize very compact circuits for implementing the static memory cell, compared with the memory cells in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks having the NDC. The peak-to-valley current ratio of the SET block is above 5 with C/sub G/=5.4C/sub T/(C/sub T/=0.1aF) at T=77K. A read and write operation of the proposed memory cell was validated with SET/CMOS hybrid simulation at T=77K. Even though the fabrication process which integrate MOSFET devices and SET block with NDC is not available, these results suggest that the proposed SET/CMOS static memory cell is suitable for a high density memory system with the low power consumption.</description><subject>CMOS memory circuits</subject><subject>CMOS technology</subject><subject>Electrons</subject><subject>Energy consumption</subject><subject>Fabrication</subject><subject>MOSFET circuits</subject><subject>Nanoscale devices</subject><subject>Read-write memory</subject><subject>Tunneling</subject><subject>Voltage</subject><isbn>0780379764</isbn><isbn>9780780379763</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tKw0AUQAdEUGs_QNzMDyS9884sXIRQH1CbReu6zExu7EiSaiYi-XsFezZnd-AQcscgZwzsaltu65wDiJxxwQD4BbkBU4Aw1mh5RZYpfcAfwiqt7DV5KOmAP7TBFN8HOmE4DvHrG-mppcfZj7Ghu_V-Vb3WO5omN8VAe-xP40wDdl26JZet6xIuz16Qt8f1vnrONvXTS1VussiMmjLkSktQGsF41urCMOYdF0UhQepCMxekapEHBVIoHZzhTgfdoLRGNdZ7sSD3_92IiIfPMfZunA_nQ_EL0W5Edw</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Bong-Hoon Lee</creator><creator>Yoon-Ha Jeong</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2003</creationdate><title>A new design technique of hybrid SET/CMOS static memory cells</title><author>Bong-Hoon Lee ; Yoon-Ha Jeong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-e2564056e07b1f68711ba23884046861ac45fe2c504356ca72a6c6de4975d9bb3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>CMOS memory circuits</topic><topic>CMOS technology</topic><topic>Electrons</topic><topic>Energy consumption</topic><topic>Fabrication</topic><topic>MOSFET circuits</topic><topic>Nanoscale devices</topic><topic>Read-write memory</topic><topic>Tunneling</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Bong-Hoon Lee</creatorcontrib><creatorcontrib>Yoon-Ha Jeong</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bong-Hoon Lee</au><au>Yoon-Ha Jeong</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A new design technique of hybrid SET/CMOS static memory cells</atitle><btitle>2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003</btitle><stitle>NANO</stitle><date>2003</date><risdate>2003</risdate><volume>2</volume><spage>674</spage><epage>677 vol. 2</epage><pages>674-677 vol. 2</pages><isbn>0780379764</isbn><isbn>9780780379763</isbn><abstract>The single electron transistor(SET)/CMOS-based static memory cell is proposed. The negative differential conductance(NDC) characteristics of SET block help to realize very compact circuits for implementing the static memory cell, compared with the memory cells in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks having the NDC. The peak-to-valley current ratio of the SET block is above 5 with C/sub G/=5.4C/sub T/(C/sub T/=0.1aF) at T=77K. A read and write operation of the proposed memory cell was validated with SET/CMOS hybrid simulation at T=77K. Even though the fabrication process which integrate MOSFET devices and SET block with NDC is not available, these results suggest that the proposed SET/CMOS static memory cell is suitable for a high density memory system with the low power consumption.</abstract><pub>IEEE</pub><doi>10.1109/NANO.2003.1231002</doi></addata></record> |
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| ispartof | 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003, 2003, Vol.2, p.674-677 vol. 2 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS memory circuits CMOS technology Electrons Energy consumption Fabrication MOSFET circuits Nanoscale devices Read-write memory Tunneling Voltage |
| title | A new design technique of hybrid SET/CMOS static memory cells |
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