Stochastic assembly of sublithographic nanoscale interfaces
We describe a technique for addressing individual nanoscale wires with microscale control wires without using lithographic-scale processing to define nanoscale dimensions. Such a scheme is necessary to exploit sublithographic nanoscale storage and computational devices. Our technique uses modulation...
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Veröffentlicht in: | IEEE transactions on nanotechnology 2003-09, Vol.2 (3), p.165-174 |
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creator | DeHon, A. Lincoln, P. Savage, J.E. |
description | We describe a technique for addressing individual nanoscale wires with microscale control wires without using lithographic-scale processing to define nanoscale dimensions. Such a scheme is necessary to exploit sublithographic nanoscale storage and computational devices. Our technique uses modulation doping to address individual nanowires and self-assembly to organize them into nanoscale-pitch decoder arrays. We show that if coded nanowires are chosen at random from a sufficiently large population, we can ensure that a large fraction of the selected nanowires have unique addresses. For example, we show that N lines can be uniquely addressed over 99% of the time using no more than /spl lceil/2.2log/sub 2/(N)/spl rceil/+11 address wires. We further show a hybrid decoder scheme that only needs to address N=O(W/sub litho-pitch//W/sub nano-pitch/) wires at a time through this stochastic scheme; as a result, the number of unique codes required for the nanowires does not grow with decoder size. We give an O(N/sup 2/) procedure to discover the addresses which are present. We also demonstrate schemes that tolerate the misalignment of nanowires which can occur during the self-assembly process. |
doi_str_mv | 10.1109/TNANO.2003.816658 |
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Such a scheme is necessary to exploit sublithographic nanoscale storage and computational devices. Our technique uses modulation doping to address individual nanowires and self-assembly to organize them into nanoscale-pitch decoder arrays. We show that if coded nanowires are chosen at random from a sufficiently large population, we can ensure that a large fraction of the selected nanowires have unique addresses. For example, we show that N lines can be uniquely addressed over 99% of the time using no more than /spl lceil/2.2log/sub 2/(N)/spl rceil/+11 address wires. We further show a hybrid decoder scheme that only needs to address N=O(W/sub litho-pitch//W/sub nano-pitch/) wires at a time through this stochastic scheme; as a result, the number of unique codes required for the nanowires does not grow with decoder size. We give an O(N/sup 2/) procedure to discover the addresses which are present. We also demonstrate schemes that tolerate the misalignment of nanowires which can occur during the self-assembly process.</description><identifier>ISSN: 1536-125X</identifier><identifier>EISSN: 1941-0085</identifier><identifier>DOI: 10.1109/TNANO.2003.816658</identifier><identifier>CODEN: ITNECU</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Assembly ; Computer science ; Decoding ; Electronics ; Epitaxial layers ; Exact sciences and technology ; Molecular electronics, nanoelectronics ; Nanoscale devices ; Nanowires ; Programmable logic arrays ; Self-assembly ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Stochastic processes ; Wires</subject><ispartof>IEEE transactions on nanotechnology, 2003-09, Vol.2 (3), p.165-174</ispartof><rights>2003 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2003</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c395t-e63ddb40893b5265bc3ac70985671d060e2e2e0a463ac936915a0bd72e9d785a3</citedby><cites>FETCH-LOGICAL-c395t-e63ddb40893b5265bc3ac70985671d060e2e2e0a463ac936915a0bd72e9d785a3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1230118$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1230118$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=15115526$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>DeHon, A.</creatorcontrib><creatorcontrib>Lincoln, P.</creatorcontrib><creatorcontrib>Savage, J.E.</creatorcontrib><title>Stochastic assembly of sublithographic nanoscale interfaces</title><title>IEEE transactions on nanotechnology</title><addtitle>TNANO</addtitle><description>We describe a technique for addressing individual nanoscale wires with microscale control wires without using lithographic-scale processing to define nanoscale dimensions. Such a scheme is necessary to exploit sublithographic nanoscale storage and computational devices. Our technique uses modulation doping to address individual nanowires and self-assembly to organize them into nanoscale-pitch decoder arrays. We show that if coded nanowires are chosen at random from a sufficiently large population, we can ensure that a large fraction of the selected nanowires have unique addresses. For example, we show that N lines can be uniquely addressed over 99% of the time using no more than /spl lceil/2.2log/sub 2/(N)/spl rceil/+11 address wires. We further show a hybrid decoder scheme that only needs to address N=O(W/sub litho-pitch//W/sub nano-pitch/) wires at a time through this stochastic scheme; as a result, the number of unique codes required for the nanowires does not grow with decoder size. We give an O(N/sup 2/) procedure to discover the addresses which are present. We also demonstrate schemes that tolerate the misalignment of nanowires which can occur during the self-assembly process.</description><subject>Applied sciences</subject><subject>Assembly</subject><subject>Computer science</subject><subject>Decoding</subject><subject>Electronics</subject><subject>Epitaxial layers</subject><subject>Exact sciences and technology</subject><subject>Molecular electronics, nanoelectronics</subject><subject>Nanoscale devices</subject><subject>Nanowires</subject><subject>Programmable logic arrays</subject><subject>Self-assembly</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Stochastic processes</subject><subject>Wires</subject><issn>1536-125X</issn><issn>1941-0085</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2003</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkM9LwzAUx4soOKd_gHgpiN4632uaNMGTDH_B2A5O8BbSNHUdXTOT9rD_3swOBpJDQt7nfXnvE0XXCBNEEA_L-dN8MUkByIQjY5SfRCMUGSYAnJ6GNyUswZR-nUcX3q8BMA_QKHr86KxeKd_VOlbem03R7GJbxb4vmrpb2W-ntqtQa1VrvVaNieu2M65S2vjL6KxSjTdXh3scfb48L6dvyWzx-j59miWaCNolhpGyLDLgghQ0ZbTQROkcBKcsxxIYmDQcUBkL_4IwgVRBUeapEWXOqSLj6H7I3Tr70xvfyU3ttWka1Rrbe5lyxsLiLIC3_8C17V0bZpMYcoMYIFmgcKC0s947U8mtqzfK7SSC3MuUfzLlXqYcZIaeu0Oy2luonGp17Y-NFJGG3QJ3M3C1MeZYTgkgcvILJx58dw</recordid><startdate>20030901</startdate><enddate>20030901</enddate><creator>DeHon, A.</creator><creator>Lincoln, P.</creator><creator>Savage, J.E.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7SR</scope><scope>7U5</scope><scope>8BQ</scope><scope>8FD</scope><scope>JG9</scope><scope>L7M</scope></search><sort><creationdate>20030901</creationdate><title>Stochastic assembly of sublithographic nanoscale interfaces</title><author>DeHon, A. ; Lincoln, P. ; Savage, J.E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c395t-e63ddb40893b5265bc3ac70985671d060e2e2e0a463ac936915a0bd72e9d785a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Applied sciences</topic><topic>Assembly</topic><topic>Computer science</topic><topic>Decoding</topic><topic>Electronics</topic><topic>Epitaxial layers</topic><topic>Exact sciences and technology</topic><topic>Molecular electronics, nanoelectronics</topic><topic>Nanoscale devices</topic><topic>Nanowires</topic><topic>Programmable logic arrays</topic><topic>Self-assembly</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Stochastic processes</topic><topic>Wires</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>DeHon, A.</creatorcontrib><creatorcontrib>Lincoln, P.</creatorcontrib><creatorcontrib>Savage, J.E.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Materials Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on nanotechnology</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DeHon, A.</au><au>Lincoln, P.</au><au>Savage, J.E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Stochastic assembly of sublithographic nanoscale interfaces</atitle><jtitle>IEEE transactions on nanotechnology</jtitle><stitle>TNANO</stitle><date>2003-09-01</date><risdate>2003</risdate><volume>2</volume><issue>3</issue><spage>165</spage><epage>174</epage><pages>165-174</pages><issn>1536-125X</issn><eissn>1941-0085</eissn><coden>ITNECU</coden><abstract>We describe a technique for addressing individual nanoscale wires with microscale control wires without using lithographic-scale processing to define nanoscale dimensions. Such a scheme is necessary to exploit sublithographic nanoscale storage and computational devices. Our technique uses modulation doping to address individual nanowires and self-assembly to organize them into nanoscale-pitch decoder arrays. We show that if coded nanowires are chosen at random from a sufficiently large population, we can ensure that a large fraction of the selected nanowires have unique addresses. For example, we show that N lines can be uniquely addressed over 99% of the time using no more than /spl lceil/2.2log/sub 2/(N)/spl rceil/+11 address wires. We further show a hybrid decoder scheme that only needs to address N=O(W/sub litho-pitch//W/sub nano-pitch/) wires at a time through this stochastic scheme; as a result, the number of unique codes required for the nanowires does not grow with decoder size. We give an O(N/sup 2/) procedure to discover the addresses which are present. We also demonstrate schemes that tolerate the misalignment of nanowires which can occur during the self-assembly process.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TNANO.2003.816658</doi><tpages>10</tpages><oa>free_for_read</oa></addata></record> |
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subjects | Applied sciences Assembly Computer science Decoding Electronics Epitaxial layers Exact sciences and technology Molecular electronics, nanoelectronics Nanoscale devices Nanowires Programmable logic arrays Self-assembly Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Stochastic processes Wires |
title | Stochastic assembly of sublithographic nanoscale interfaces |
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