Floating point unit generation and evaluation for FPGAs
Most commercial and academic floating point libraries for FPGAs (field programmable gate arrays) provide only a small fraction of all possible floating point units. In contrast, the floating point unit generation approach outlined in this paper allows for the creation of a vast collection of floatin...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 194 |
|---|---|
| container_issue | |
| container_start_page | 185 |
| container_title | |
| container_volume | |
| creator | Jian Liang Tessier, R. Mencer, O. |
| description | Most commercial and academic floating point libraries for FPGAs (field programmable gate arrays) provide only a small fraction of all possible floating point units. In contrast, the floating point unit generation approach outlined in this paper allows for the creation of a vast collection of floating point units with differing throughput, latency, and area characteristics. Given performance requirements, our generation tool automatically chooses the proper implementation algorithm and architecture to create a compliant floating point unit. Our approach is fully integrated into standard C++ using ASC, a stream compiler for FPGAs, and the PAM-Blox II module generation environment. The floating point units created by our approach exhibit a factor of two latency improvement versus commercial FPGA floating point units, while consuming only half of the FPGA logic area. |
| doi_str_mv | 10.1109/FPGA.2003.1227254 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1227254</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1227254</ieee_id><sourcerecordid>1227254</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-49b903e0ca5395dcc465c3cd20b933857d0e8518fe4d448ce9a6f1c8d661714f3</originalsourceid><addsrcrecordid>eNotj09LAzEUxAMiqLUfQLzkC-yal__vWIpbhYIe2nNJk7clsmbL7lbw21tp5zLM7zDDMPYEogYQ-NJ8rha1FELVIKWTRt-wB-EsGkCH8o7Nx_FLnKVQOyPvmWu6Pky5HPixz2Xip5InfqBCw5n2hYeSOP2E7nSJbT_w_4nxkd22oRtpfvUZ2zavm-Vbtf5YvS8X6yqDM1OlcY9CkYjBKDQpRm1NVDFJsUelvHFJkDfgW9JJax8Jg20h-mQtONCtmrHnS28mot1xyN9h-N1dv6k_vzNDxg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Floating point unit generation and evaluation for FPGAs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Jian Liang ; Tessier, R. ; Mencer, O.</creator><creatorcontrib>Jian Liang ; Tessier, R. ; Mencer, O.</creatorcontrib><description>Most commercial and academic floating point libraries for FPGAs (field programmable gate arrays) provide only a small fraction of all possible floating point units. In contrast, the floating point unit generation approach outlined in this paper allows for the creation of a vast collection of floating point units with differing throughput, latency, and area characteristics. Given performance requirements, our generation tool automatically chooses the proper implementation algorithm and architecture to create a compliant floating point unit. Our approach is fully integrated into standard C++ using ASC, a stream compiler for FPGAs, and the PAM-Blox II module generation environment. The floating point units created by our approach exhibit a factor of two latency improvement versus commercial FPGA floating point units, while consuming only half of the FPGA logic area.</description><identifier>ISBN: 0769519792</identifier><identifier>ISBN: 9780769519791</identifier><identifier>DOI: 10.1109/FPGA.2003.1227254</identifier><language>eng</language><publisher>IEEE</publisher><subject>Algorithm design and analysis ; Application software ; Character generation ; Delay ; Educational institutions ; Field programmable gate arrays ; Libraries ; Logic ; Parallel processing ; Throughput</subject><ispartof>11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003, 2003, p.185-194</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1227254$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1227254$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jian Liang</creatorcontrib><creatorcontrib>Tessier, R.</creatorcontrib><creatorcontrib>Mencer, O.</creatorcontrib><title>Floating point unit generation and evaluation for FPGAs</title><title>11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003</title><addtitle>FPGA</addtitle><description>Most commercial and academic floating point libraries for FPGAs (field programmable gate arrays) provide only a small fraction of all possible floating point units. In contrast, the floating point unit generation approach outlined in this paper allows for the creation of a vast collection of floating point units with differing throughput, latency, and area characteristics. Given performance requirements, our generation tool automatically chooses the proper implementation algorithm and architecture to create a compliant floating point unit. Our approach is fully integrated into standard C++ using ASC, a stream compiler for FPGAs, and the PAM-Blox II module generation environment. The floating point units created by our approach exhibit a factor of two latency improvement versus commercial FPGA floating point units, while consuming only half of the FPGA logic area.</description><subject>Algorithm design and analysis</subject><subject>Application software</subject><subject>Character generation</subject><subject>Delay</subject><subject>Educational institutions</subject><subject>Field programmable gate arrays</subject><subject>Libraries</subject><subject>Logic</subject><subject>Parallel processing</subject><subject>Throughput</subject><isbn>0769519792</isbn><isbn>9780769519791</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj09LAzEUxAMiqLUfQLzkC-yal__vWIpbhYIe2nNJk7clsmbL7lbw21tp5zLM7zDDMPYEogYQ-NJ8rha1FELVIKWTRt-wB-EsGkCH8o7Nx_FLnKVQOyPvmWu6Pky5HPixz2Xip5InfqBCw5n2hYeSOP2E7nSJbT_w_4nxkd22oRtpfvUZ2zavm-Vbtf5YvS8X6yqDM1OlcY9CkYjBKDQpRm1NVDFJsUelvHFJkDfgW9JJax8Jg20h-mQtONCtmrHnS28mot1xyN9h-N1dv6k_vzNDxg</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Jian Liang</creator><creator>Tessier, R.</creator><creator>Mencer, O.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2003</creationdate><title>Floating point unit generation and evaluation for FPGAs</title><author>Jian Liang ; Tessier, R. ; Mencer, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-49b903e0ca5395dcc465c3cd20b933857d0e8518fe4d448ce9a6f1c8d661714f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Algorithm design and analysis</topic><topic>Application software</topic><topic>Character generation</topic><topic>Delay</topic><topic>Educational institutions</topic><topic>Field programmable gate arrays</topic><topic>Libraries</topic><topic>Logic</topic><topic>Parallel processing</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>Jian Liang</creatorcontrib><creatorcontrib>Tessier, R.</creatorcontrib><creatorcontrib>Mencer, O.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jian Liang</au><au>Tessier, R.</au><au>Mencer, O.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Floating point unit generation and evaluation for FPGAs</atitle><btitle>11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003</btitle><stitle>FPGA</stitle><date>2003</date><risdate>2003</risdate><spage>185</spage><epage>194</epage><pages>185-194</pages><isbn>0769519792</isbn><isbn>9780769519791</isbn><abstract>Most commercial and academic floating point libraries for FPGAs (field programmable gate arrays) provide only a small fraction of all possible floating point units. In contrast, the floating point unit generation approach outlined in this paper allows for the creation of a vast collection of floating point units with differing throughput, latency, and area characteristics. Given performance requirements, our generation tool automatically chooses the proper implementation algorithm and architecture to create a compliant floating point unit. Our approach is fully integrated into standard C++ using ASC, a stream compiler for FPGAs, and the PAM-Blox II module generation environment. The floating point units created by our approach exhibit a factor of two latency improvement versus commercial FPGA floating point units, while consuming only half of the FPGA logic area.</abstract><pub>IEEE</pub><doi>10.1109/FPGA.2003.1227254</doi><tpages>10</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 0769519792 |
| ispartof | 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003, 2003, p.185-194 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_1227254 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Application software Character generation Delay Educational institutions Field programmable gate arrays Libraries Logic Parallel processing Throughput |
| title | Floating point unit generation and evaluation for FPGAs |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T22%3A43%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Floating%20point%20unit%20generation%20and%20evaluation%20for%20FPGAs&rft.btitle=11th%20Annual%20IEEE%20Symposium%20on%20Field-Programmable%20Custom%20Computing%20Machines,%202003.%20FCCM%202003&rft.au=Jian%20Liang&rft.date=2003&rft.spage=185&rft.epage=194&rft.pages=185-194&rft.isbn=0769519792&rft.isbn_list=9780769519791&rft_id=info:doi/10.1109/FPGA.2003.1227254&rft_dat=%3Cieee_6IE%3E1227254%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1227254&rfr_iscdi=true |