EPD time delay as WSix stack down gate etching in DPS+ chamber

Device makers want to make higher density chips as devices shrink, especially WSix polystack down is one of the key issues. However, EPD (end point detection) time delay was happened in DPS+ poly chamber which is a barrier to achieve device shrink because EPD time delay killed test pattern and next...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yong Deuk Ko, Hui-Gon Chun, Jing-Hyuk Lee, Jae-Ho Byun, Jae-Pil Jeon, Yong-Hwa Song, Tong-Yul Cho
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Delay effects Electron emission Electron optics Etching Optical microscopy Plasma applications Scanning electron microscopy Spectroscopy Stimulated emission Testing
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