Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond
90 nm DRAM technology and beyond requires the robust memory cell capacitor structure in order to increase cell capacitance for high performance and low power applications. Thus, the cell technology must have the feature of high capacitance of memory cell capacitor while maintaining its mechanical st...
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| creator | Jaegoo Lee Yongseok Ahn Yangkeun Park Minsang Kim Dongjun Lee Kyuhyun Lee Changhyun Cho Taeyoung Chung Kinam Kim |
| description | 90 nm DRAM technology and beyond requires the robust memory cell capacitor structure in order to increase cell capacitance for high performance and low power applications. Thus, the cell technology must have the feature of high capacitance of memory cell capacitor while maintaining its mechanical stability. To accomplish these purposes, we develop the multi-stack storage node structure whose enlarged bottom size of OCS(One Cylindrical Storage node) can give much better mechanical stability of the capacitor than that of the conventional capacitor. Using Al/sub 2/O/sub 3//HfO/sub 2/ dielectric material together with this structure can give high cell capacitance 30fF/cell and low leakage current less than 1fA/cell. |
| doi_str_mv | 10.1109/VLSIT.2003.1221084 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1221084</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1221084</ieee_id><sourcerecordid>1221084</sourcerecordid><originalsourceid>FETCH-ieee_primary_12210843</originalsourceid><addsrcrecordid>eNp9jr9uwjAYxC0hpKKSFyjL9wIE23FEMldFIDFBxIqM85G49Z_Idoa8fTMwc8udfnfDEfLFaM4YrXe38_XU5JzSImecM1qJBcnqfSWqmjFBi6L8IFmMv3SWKAUv-Yr4i3-MMYFF68MECo0BJQepdPIBxqhdB3Y0SW9jkuoP4oxlh-B8i_CcJ73uehgwzNlKpxC0g5qCs5BQ9c4b300gXQsPnLxr12T5lCZi9vJPsjn8NN_HrUbE-xC0lWG6v-4X79t_9uZK_A</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Jaegoo Lee ; Yongseok Ahn ; Yangkeun Park ; Minsang Kim ; Dongjun Lee ; Kyuhyun Lee ; Changhyun Cho ; Taeyoung Chung ; Kinam Kim</creator><creatorcontrib>Jaegoo Lee ; Yongseok Ahn ; Yangkeun Park ; Minsang Kim ; Dongjun Lee ; Kyuhyun Lee ; Changhyun Cho ; Taeyoung Chung ; Kinam Kim</creatorcontrib><description>90 nm DRAM technology and beyond requires the robust memory cell capacitor structure in order to increase cell capacitance for high performance and low power applications. Thus, the cell technology must have the feature of high capacitance of memory cell capacitor while maintaining its mechanical stability. To accomplish these purposes, we develop the multi-stack storage node structure whose enlarged bottom size of OCS(One Cylindrical Storage node) can give much better mechanical stability of the capacitor than that of the conventional capacitor. Using Al/sub 2/O/sub 3//HfO/sub 2/ dielectric material together with this structure can give high cell capacitance 30fF/cell and low leakage current less than 1fA/cell.</description><identifier>ISBN: 9784891140335</identifier><identifier>ISBN: 489114033X</identifier><identifier>DOI: 10.1109/VLSIT.2003.1221084</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; Capacitors ; Costs ; Etching ; Fabrication ; Intelligent networks ; Lithography ; Random access memory ; Robustness ; Stability</subject><ispartof>2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407), 2003, p.57-58</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1221084$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1221084$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jaegoo Lee</creatorcontrib><creatorcontrib>Yongseok Ahn</creatorcontrib><creatorcontrib>Yangkeun Park</creatorcontrib><creatorcontrib>Minsang Kim</creatorcontrib><creatorcontrib>Dongjun Lee</creatorcontrib><creatorcontrib>Kyuhyun Lee</creatorcontrib><creatorcontrib>Changhyun Cho</creatorcontrib><creatorcontrib>Taeyoung Chung</creatorcontrib><creatorcontrib>Kinam Kim</creatorcontrib><title>Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond</title><title>2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)</title><addtitle>VLSIT</addtitle><description>90 nm DRAM technology and beyond requires the robust memory cell capacitor structure in order to increase cell capacitance for high performance and low power applications. Thus, the cell technology must have the feature of high capacitance of memory cell capacitor while maintaining its mechanical stability. To accomplish these purposes, we develop the multi-stack storage node structure whose enlarged bottom size of OCS(One Cylindrical Storage node) can give much better mechanical stability of the capacitor than that of the conventional capacitor. Using Al/sub 2/O/sub 3//HfO/sub 2/ dielectric material together with this structure can give high cell capacitance 30fF/cell and low leakage current less than 1fA/cell.</description><subject>Capacitance</subject><subject>Capacitors</subject><subject>Costs</subject><subject>Etching</subject><subject>Fabrication</subject><subject>Intelligent networks</subject><subject>Lithography</subject><subject>Random access memory</subject><subject>Robustness</subject><subject>Stability</subject><isbn>9784891140335</isbn><isbn>489114033X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jr9uwjAYxC0hpKKSFyjL9wIE23FEMldFIDFBxIqM85G49Z_Idoa8fTMwc8udfnfDEfLFaM4YrXe38_XU5JzSImecM1qJBcnqfSWqmjFBi6L8IFmMv3SWKAUv-Yr4i3-MMYFF68MECo0BJQepdPIBxqhdB3Y0SW9jkuoP4oxlh-B8i_CcJ73uehgwzNlKpxC0g5qCs5BQ9c4b300gXQsPnLxr12T5lCZi9vJPsjn8NN_HrUbE-xC0lWG6v-4X79t_9uZK_A</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Jaegoo Lee</creator><creator>Yongseok Ahn</creator><creator>Yangkeun Park</creator><creator>Minsang Kim</creator><creator>Dongjun Lee</creator><creator>Kyuhyun Lee</creator><creator>Changhyun Cho</creator><creator>Taeyoung Chung</creator><creator>Kinam Kim</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2003</creationdate><title>Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond</title><author>Jaegoo Lee ; Yongseok Ahn ; Yangkeun Park ; Minsang Kim ; Dongjun Lee ; Kyuhyun Lee ; Changhyun Cho ; Taeyoung Chung ; Kinam Kim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_12210843</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Capacitance</topic><topic>Capacitors</topic><topic>Costs</topic><topic>Etching</topic><topic>Fabrication</topic><topic>Intelligent networks</topic><topic>Lithography</topic><topic>Random access memory</topic><topic>Robustness</topic><topic>Stability</topic><toplevel>online_resources</toplevel><creatorcontrib>Jaegoo Lee</creatorcontrib><creatorcontrib>Yongseok Ahn</creatorcontrib><creatorcontrib>Yangkeun Park</creatorcontrib><creatorcontrib>Minsang Kim</creatorcontrib><creatorcontrib>Dongjun Lee</creatorcontrib><creatorcontrib>Kyuhyun Lee</creatorcontrib><creatorcontrib>Changhyun Cho</creatorcontrib><creatorcontrib>Taeyoung Chung</creatorcontrib><creatorcontrib>Kinam Kim</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jaegoo Lee</au><au>Yongseok Ahn</au><au>Yangkeun Park</au><au>Minsang Kim</au><au>Dongjun Lee</au><au>Kyuhyun Lee</au><au>Changhyun Cho</au><au>Taeyoung Chung</au><au>Kinam Kim</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond</atitle><btitle>2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)</btitle><stitle>VLSIT</stitle><date>2003</date><risdate>2003</risdate><spage>57</spage><epage>58</epage><pages>57-58</pages><isbn>9784891140335</isbn><isbn>489114033X</isbn><abstract>90 nm DRAM technology and beyond requires the robust memory cell capacitor structure in order to increase cell capacitance for high performance and low power applications. Thus, the cell technology must have the feature of high capacitance of memory cell capacitor while maintaining its mechanical stability. To accomplish these purposes, we develop the multi-stack storage node structure whose enlarged bottom size of OCS(One Cylindrical Storage node) can give much better mechanical stability of the capacitor than that of the conventional capacitor. Using Al/sub 2/O/sub 3//HfO/sub 2/ dielectric material together with this structure can give high cell capacitance 30fF/cell and low leakage current less than 1fA/cell.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.2003.1221084</doi></addata></record> |
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| identifier | ISBN: 9784891140335 |
| ispartof | 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407), 2003, p.57-58 |
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| language | eng |
| recordid | cdi_ieee_primary_1221084 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitance Capacitors Costs Etching Fabrication Intelligent networks Lithography Random access memory Robustness Stability |
| title | Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T14%3A13%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Robust%20memory%20cell%20capacitor%20using%20multi-stack%20storage%20node%20for%20high%20performance%20in%2090%20nm%20technology%20and%20beyond&rft.btitle=2003%20Symposium%20on%20VLSI%20Technology.%20Digest%20of%20Technical%20Papers%20(IEEE%20Cat.%20No.03CH37407)&rft.au=Jaegoo%20Lee&rft.date=2003&rft.spage=57&rft.epage=58&rft.pages=57-58&rft.isbn=9784891140335&rft.isbn_list=489114033X&rft_id=info:doi/10.1109/VLSIT.2003.1221084&rft_dat=%3Cieee_6IE%3E1221084%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1221084&rfr_iscdi=true |