Barrier-first integration for improved reliability in copper dual damascene interconnects
A new PVD barrier process is demonstrated that eliminates critical dimension (CD) loss and copper contamination of intra-layer dielectric (ILD) caused by conventional argon sputter precleans. In this process, a layer of Ta(N) is first deposited to protect the via sidewalls from contamination, then a...
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| creator | Alers, G.B. Rozbicki, R.T. Harm, G.J. Kailasam, S.K. Ray, G.W. Danek, M. |
| description | A new PVD barrier process is demonstrated that eliminates critical dimension (CD) loss and copper contamination of intra-layer dielectric (ILD) caused by conventional argon sputter precleans. In this process, a layer of Ta(N) is first deposited to protect the via sidewalls from contamination, then an RF bias is applied to the wafer during subsequent barrier deposition such that there is a net etch (resputter) from the bottom of the vias. The resputter step allows effective removal of Cu oxide and etch-residues without contamination of the dielectric with resputtered copper, and without faceting of the ILD. This barrier-first scheme improves via resistance, ILD reliability, via stress migration and electromigration performance relative to a conventional argon sputter preclean. |
| doi_str_mv | 10.1109/IITC.2003.1219702 |
| format | Conference Proceeding |
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In this process, a layer of Ta(N) is first deposited to protect the via sidewalls from contamination, then an RF bias is applied to the wafer during subsequent barrier deposition such that there is a net etch (resputter) from the bottom of the vias. The resputter step allows effective removal of Cu oxide and etch-residues without contamination of the dielectric with resputtered copper, and without faceting of the ILD. This barrier-first scheme improves via resistance, ILD reliability, via stress migration and electromigration performance relative to a conventional argon sputter preclean.</description><identifier>ISBN: 9780780377974</identifier><identifier>ISBN: 0780377974</identifier><identifier>DOI: 10.1109/IITC.2003.1219702</identifier><language>eng</language><publisher>IEEE</publisher><subject>Argon ; Atherosclerosis ; Contamination ; Copper ; Dielectric losses ; Electromigration ; Protection ; Radio frequency ; Sputter etching ; Stress</subject><ispartof>Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. 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This barrier-first scheme improves via resistance, ILD reliability, via stress migration and electromigration performance relative to a conventional argon sputter preclean.</description><subject>Argon</subject><subject>Atherosclerosis</subject><subject>Contamination</subject><subject>Copper</subject><subject>Dielectric losses</subject><subject>Electromigration</subject><subject>Protection</subject><subject>Radio frequency</subject><subject>Sputter etching</subject><subject>Stress</subject><isbn>9780780377974</isbn><isbn>0780377974</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotUMlKxEAUbBBBGfMB4qV_ILG3mPRRg0tgYC7jwdPw8vr10JKN7ijM3xt1ioKqQ1UdirFbKQophb1v231TKCF0IZW0lVAXLLNVLVbqqrKVuWJZSp9ihbalNvKafTxBjIFi7kNMCw_jQscIS5hG7qfIwzDH6Zscj9QH6EIfltMa4jjNM0XuvqDnDgZISCP9tSNO40i4pBt26aFPlJ11w95fnvfNW77dvbbN4zY_Ki2W3Piyk16hRBJWWdUhWKRamM451YHxzqJQziPoEpDKB-NsXaMXv1bXSm_Y3f9uIKLDHMMA8XQ4H6B_AGPyU6M</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Alers, G.B.</creator><creator>Rozbicki, R.T.</creator><creator>Harm, G.J.</creator><creator>Kailasam, S.K.</creator><creator>Ray, G.W.</creator><creator>Danek, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2003</creationdate><title>Barrier-first integration for improved reliability in copper dual damascene interconnects</title><author>Alers, G.B. ; Rozbicki, R.T. ; Harm, G.J. ; Kailasam, S.K. ; Ray, G.W. ; Danek, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-g230t-4f5b1f2c1ce09292bca9ce804bdd2ba4fd9c02dfca35ace564d988cf0e5643823</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Argon</topic><topic>Atherosclerosis</topic><topic>Contamination</topic><topic>Copper</topic><topic>Dielectric losses</topic><topic>Electromigration</topic><topic>Protection</topic><topic>Radio frequency</topic><topic>Sputter etching</topic><topic>Stress</topic><toplevel>online_resources</toplevel><creatorcontrib>Alers, G.B.</creatorcontrib><creatorcontrib>Rozbicki, R.T.</creatorcontrib><creatorcontrib>Harm, G.J.</creatorcontrib><creatorcontrib>Kailasam, S.K.</creatorcontrib><creatorcontrib>Ray, G.W.</creatorcontrib><creatorcontrib>Danek, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Alers, G.B.</au><au>Rozbicki, R.T.</au><au>Harm, G.J.</au><au>Kailasam, S.K.</au><au>Ray, G.W.</au><au>Danek, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Barrier-first integration for improved reliability in copper dual damascene interconnects</atitle><btitle>Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)</btitle><stitle>IITC</stitle><date>2003</date><risdate>2003</risdate><spage>27</spage><epage>29</epage><pages>27-29</pages><isbn>9780780377974</isbn><isbn>0780377974</isbn><abstract>A new PVD barrier process is demonstrated that eliminates critical dimension (CD) loss and copper contamination of intra-layer dielectric (ILD) caused by conventional argon sputter precleans. In this process, a layer of Ta(N) is first deposited to protect the via sidewalls from contamination, then an RF bias is applied to the wafer during subsequent barrier deposition such that there is a net etch (resputter) from the bottom of the vias. The resputter step allows effective removal of Cu oxide and etch-residues without contamination of the dielectric with resputtered copper, and without faceting of the ILD. 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| identifier | ISBN: 9780780377974 |
| ispartof | Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695), 2003, p.27-29 |
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| language | eng |
| recordid | cdi_ieee_primary_1219702 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Argon Atherosclerosis Contamination Copper Dielectric losses Electromigration Protection Radio frequency Sputter etching Stress |
| title | Barrier-first integration for improved reliability in copper dual damascene interconnects |
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