Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process
This paper investigates the electrostatic discharge (ESD) characteristics of the silicon-germanium heterojunction bipolar transistor (SiGe HBT) in a 0.18-μm SiGe BiCMOS process. According to this letter, the open base configuration in the SiGe HBT has lower trigger voltage and higher ESD robustness...
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| Veröffentlicht in: | IEEE electron device letters 2003-03, Vol.24 (3), p.168-170, Article 168 |
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| container_end_page | 170 |
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| container_issue | 3 |
| container_start_page | 168 |
| container_title | IEEE electron device letters |
| container_volume | 24 |
| creator | Shiao-Shien Chen Tung-Yang Chen Tien-Hao Tang Shao-Chang Huang Hsu, T.-L. Hua-Chou Tseng Jen-Kon Chen Chiu-Hsiang Chou |
| description | This paper investigates the electrostatic discharge (ESD) characteristics of the silicon-germanium heterojunction bipolar transistor (SiGe HBT) in a 0.18-μm SiGe BiCMOS process. According to this letter, the open base configuration in the SiGe HBT has lower trigger voltage and higher ESD robustness than a common base configuration. As compared to the gate-grounded NMOS and PMOS in a bulk CMOS process, the SiGe HBT has a higher ESD efficiency from the layout area point of view. Additionally, any trigger biases used to improve the ESD robustness of the SiGe HBT are observed as invalid, and even they can work successfully in bulk CMOS process. |
| doi_str_mv | 10.1109/LED.2003.809534 |
| format | Article |
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According to this letter, the open base configuration in the SiGe HBT has lower trigger voltage and higher ESD robustness than a common base configuration. As compared to the gate-grounded NMOS and PMOS in a bulk CMOS process, the SiGe HBT has a higher ESD efficiency from the layout area point of view. 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According to this letter, the open base configuration in the SiGe HBT has lower trigger voltage and higher ESD robustness than a common base configuration. As compared to the gate-grounded NMOS and PMOS in a bulk CMOS process, the SiGe HBT has a higher ESD efficiency from the layout area point of view. Additionally, any trigger biases used to improve the ESD robustness of the SiGe HBT are observed as invalid, and even they can work successfully in bulk CMOS process.</description><subject>BiCMOS integrated circuits</subject><subject>CMOS</subject><subject>CMOS process</subject><subject>Devices</subject><subject>Electric potential</subject><subject>Electrostatic discharge</subject><subject>Electrostatic discharges</subject><subject>Germanium silicon alloys</subject><subject>Heterojunction bipolar transistors</subject><subject>MOS devices</subject><subject>Robustness</subject><subject>Silicon germanides</subject><subject>Silicon germanium</subject><subject>Stress</subject><subject>Voltage</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2003</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kLtOwzAUhi0EEqUwM7B4Y0p7fEvikV5oKxV1aJkt13EqozQpdorEu_EMPBMuQUJiYDrD-b_z63wI3RIYEAJyuJxOBhSADXKQgvEz1CNC5AmIlJ2jHmScJIxAeomuQngBIJxnvIdWi_rNhtbtdOuaGjcl1njtZhbPRxtcHL2rd3i6nuDQehsCdnXcx8I8-fzYd8GRGz-t1vjgGxMT1-ii1FWwNz-zj54fp5vxPFmuZovxwzIxFNI2yazZ8tzK0hSaS0kLW0gwlGSaFIILKyzTOmeUpkLzLBc0k8BZYcuCayK2Oeuj--5u7H09xg_U3gVjq0rXtjkGJYFkRNIsjclhlzS-CcHbUh2822v_rgiokzkVzamTOdWZi4T4QxjXfvtpvXbVP9xdxzlr7W8LBSpIyr4ALsB4eQ</recordid><startdate>200303</startdate><enddate>200303</enddate><creator>Shiao-Shien Chen</creator><creator>Tung-Yang Chen</creator><creator>Tien-Hao Tang</creator><creator>Shao-Chang Huang</creator><creator>Hsu, T.-L.</creator><creator>Hua-Chou Tseng</creator><creator>Jen-Kon Chen</creator><creator>Chiu-Hsiang Chou</creator><general>IEEE</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>L7M</scope></search><sort><creationdate>200303</creationdate><title>Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process</title><author>Shiao-Shien Chen ; Tung-Yang Chen ; Tien-Hao Tang ; Shao-Chang Huang ; Hsu, T.-L. ; Hua-Chou Tseng ; Jen-Kon Chen ; Chiu-Hsiang Chou</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c206t-7ecb48e9fcda4992ded90c217a1d545e5e3aa832265a4785279043defd4a15b83</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2003</creationdate><topic>BiCMOS integrated circuits</topic><topic>CMOS</topic><topic>CMOS process</topic><topic>Devices</topic><topic>Electric potential</topic><topic>Electrostatic discharge</topic><topic>Electrostatic discharges</topic><topic>Germanium silicon alloys</topic><topic>Heterojunction bipolar transistors</topic><topic>MOS devices</topic><topic>Robustness</topic><topic>Silicon germanides</topic><topic>Silicon germanium</topic><topic>Stress</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Shiao-Shien Chen</creatorcontrib><creatorcontrib>Tung-Yang Chen</creatorcontrib><creatorcontrib>Tien-Hao Tang</creatorcontrib><creatorcontrib>Shao-Chang Huang</creatorcontrib><creatorcontrib>Hsu, T.-L.</creatorcontrib><creatorcontrib>Hua-Chou Tseng</creatorcontrib><creatorcontrib>Jen-Kon Chen</creatorcontrib><creatorcontrib>Chiu-Hsiang Chou</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shiao-Shien Chen</au><au>Tung-Yang Chen</au><au>Tien-Hao Tang</au><au>Shao-Chang Huang</au><au>Hsu, T.-L.</au><au>Hua-Chou Tseng</au><au>Jen-Kon Chen</au><au>Chiu-Hsiang Chou</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2003-03</date><risdate>2003</risdate><volume>24</volume><issue>3</issue><spage>168</spage><epage>170</epage><pages>168-170</pages><artnum>168</artnum><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>This paper investigates the electrostatic discharge (ESD) characteristics of the silicon-germanium heterojunction bipolar transistor (SiGe HBT) in a 0.18-μm SiGe BiCMOS process. According to this letter, the open base configuration in the SiGe HBT has lower trigger voltage and higher ESD robustness than a common base configuration. As compared to the gate-grounded NMOS and PMOS in a bulk CMOS process, the SiGe HBT has a higher ESD efficiency from the layout area point of view. Additionally, any trigger biases used to improve the ESD robustness of the SiGe HBT are observed as invalid, and even they can work successfully in bulk CMOS process.</abstract><pub>IEEE</pub><doi>10.1109/LED.2003.809534</doi><tpages>3</tpages></addata></record> |
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| issn | 0741-3106 1558-0563 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | BiCMOS integrated circuits CMOS CMOS process Devices Electric potential Electrostatic discharge Electrostatic discharges Germanium silicon alloys Heterojunction bipolar transistors MOS devices Robustness Silicon germanides Silicon germanium Stress Voltage |
| title | Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process |
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