Jitter transfer characteristics of delay-locked loops - theories and design techniques

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a z-domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is t...

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Veröffentlicht in:IEEE journal of solid-state circuits 2003-04, Vol.38 (4), p.614-621
Hauptverfasser: Lee, M.-J.E., Dally, W.J., Greer, T., Hiok-Tiaq Ng, Farjad-Rad, R., Poulton, J., Senthinathan, R.
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Sprache:eng
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