High speed electrical performance comparison between bump with RDL and wire bond technologies
As the chip clock rate keeps increasing, the electrical performance of wire bond and bump connections which are using in advanced packaging is becoming the important consideration while choosing the package solution for high-speed devices. In this paper, the electrical performance of wire bond techn...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 88 |
|---|---|
| container_issue | |
| container_start_page | 83 |
| container_title | |
| container_volume | |
| creator | Chi-Tsung Chiu Sung-Mao Wu Chi-Ping Hung |
| description | As the chip clock rate keeps increasing, the electrical performance of wire bond and bump connections which are using in advanced packaging is becoming the important consideration while choosing the package solution for high-speed devices. In this paper, the electrical performance of wire bond technology and bump with RDL (redistribution layer) technology is presented. By using full-wave 3D electromagnetic simulators, the experimental results, including the passive parasitic parameter analysis (AC resistance, inductance and capacitance) and scattering parameter analysis are presented. Discussions on the rise time, cross talk noise, and propagation delay for a 10 Gbit/s signal are also included. |
| doi_str_mv | 10.1109/EMAP.2002.1188817 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1188817</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1188817</ieee_id><sourcerecordid>1188817</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-67d68da3d5be7ef1a1a10eb53bae520f1dee912132ed6efb34d6a2828bdaf6de3</originalsourceid><addsrcrecordid>eNotkM1KxDAAhAMiqOs-gHjJC3TNT9ukx2VdXaGiiIIXWZJmuo20TUkri29vwZ05zHyXOQwhN5ytOGfF3fZ5_boSjIkZtdZcnZErpjSTKtfi84Isx_GbzUrTTKjiknzt_KGh4wA4ihbVFH1lWjog1iF2pq9Aq9ANJvox9NRiOgJz_nQDPfqpoW_3JTW9myGC2jC3CVXThzYcPMZrcl6bdsTylAvy8bB93-yS8uXxabMuE89VNiW5crl2RrrMQqHmZjaDzaQ1yASruQMKLrgUcDlqK1OXG6GFts7UuYNckNv_XQ9gP0Tfmfi7Pz0g_wCoXlQC</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>High speed electrical performance comparison between bump with RDL and wire bond technologies</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Chi-Tsung Chiu ; Sung-Mao Wu ; Chi-Ping Hung</creator><creatorcontrib>Chi-Tsung Chiu ; Sung-Mao Wu ; Chi-Ping Hung</creatorcontrib><description>As the chip clock rate keeps increasing, the electrical performance of wire bond and bump connections which are using in advanced packaging is becoming the important consideration while choosing the package solution for high-speed devices. In this paper, the electrical performance of wire bond technology and bump with RDL (redistribution layer) technology is presented. By using full-wave 3D electromagnetic simulators, the experimental results, including the passive parasitic parameter analysis (AC resistance, inductance and capacitance) and scattering parameter analysis are presented. Discussions on the rise time, cross talk noise, and propagation delay for a 10 Gbit/s signal are also included.</description><identifier>ISBN: 078037682X</identifier><identifier>ISBN: 9780780376823</identifier><identifier>DOI: 10.1109/EMAP.2002.1188817</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analytical models ; Bonding ; Clocks ; Electric resistance ; Electromagnetic analysis ; Electromagnetic induction ; Electromagnetic scattering ; Inductance ; Packaging ; Wire</subject><ispartof>Proceedings of the 4th International Symposium on Electronic Materials and Packaging, 2002, 2002, p.83-88</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1188817$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,4047,4048,27923,54918</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1188817$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chi-Tsung Chiu</creatorcontrib><creatorcontrib>Sung-Mao Wu</creatorcontrib><creatorcontrib>Chi-Ping Hung</creatorcontrib><title>High speed electrical performance comparison between bump with RDL and wire bond technologies</title><title>Proceedings of the 4th International Symposium on Electronic Materials and Packaging, 2002</title><addtitle>EMAP</addtitle><description>As the chip clock rate keeps increasing, the electrical performance of wire bond and bump connections which are using in advanced packaging is becoming the important consideration while choosing the package solution for high-speed devices. In this paper, the electrical performance of wire bond technology and bump with RDL (redistribution layer) technology is presented. By using full-wave 3D electromagnetic simulators, the experimental results, including the passive parasitic parameter analysis (AC resistance, inductance and capacitance) and scattering parameter analysis are presented. Discussions on the rise time, cross talk noise, and propagation delay for a 10 Gbit/s signal are also included.</description><subject>Analytical models</subject><subject>Bonding</subject><subject>Clocks</subject><subject>Electric resistance</subject><subject>Electromagnetic analysis</subject><subject>Electromagnetic induction</subject><subject>Electromagnetic scattering</subject><subject>Inductance</subject><subject>Packaging</subject><subject>Wire</subject><isbn>078037682X</isbn><isbn>9780780376823</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2002</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkM1KxDAAhAMiqOs-gHjJC3TNT9ukx2VdXaGiiIIXWZJmuo20TUkri29vwZ05zHyXOQwhN5ytOGfF3fZ5_boSjIkZtdZcnZErpjSTKtfi84Isx_GbzUrTTKjiknzt_KGh4wA4ihbVFH1lWjog1iF2pq9Aq9ANJvox9NRiOgJz_nQDPfqpoW_3JTW9myGC2jC3CVXThzYcPMZrcl6bdsTylAvy8bB93-yS8uXxabMuE89VNiW5crl2RrrMQqHmZjaDzaQ1yASruQMKLrgUcDlqK1OXG6GFts7UuYNckNv_XQ9gP0Tfmfi7Pz0g_wCoXlQC</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>Chi-Tsung Chiu</creator><creator>Sung-Mao Wu</creator><creator>Chi-Ping Hung</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2002</creationdate><title>High speed electrical performance comparison between bump with RDL and wire bond technologies</title><author>Chi-Tsung Chiu ; Sung-Mao Wu ; Chi-Ping Hung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-67d68da3d5be7ef1a1a10eb53bae520f1dee912132ed6efb34d6a2828bdaf6de3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Analytical models</topic><topic>Bonding</topic><topic>Clocks</topic><topic>Electric resistance</topic><topic>Electromagnetic analysis</topic><topic>Electromagnetic induction</topic><topic>Electromagnetic scattering</topic><topic>Inductance</topic><topic>Packaging</topic><topic>Wire</topic><toplevel>online_resources</toplevel><creatorcontrib>Chi-Tsung Chiu</creatorcontrib><creatorcontrib>Sung-Mao Wu</creatorcontrib><creatorcontrib>Chi-Ping Hung</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chi-Tsung Chiu</au><au>Sung-Mao Wu</au><au>Chi-Ping Hung</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High speed electrical performance comparison between bump with RDL and wire bond technologies</atitle><btitle>Proceedings of the 4th International Symposium on Electronic Materials and Packaging, 2002</btitle><stitle>EMAP</stitle><date>2002</date><risdate>2002</risdate><spage>83</spage><epage>88</epage><pages>83-88</pages><isbn>078037682X</isbn><isbn>9780780376823</isbn><abstract>As the chip clock rate keeps increasing, the electrical performance of wire bond and bump connections which are using in advanced packaging is becoming the important consideration while choosing the package solution for high-speed devices. In this paper, the electrical performance of wire bond technology and bump with RDL (redistribution layer) technology is presented. By using full-wave 3D electromagnetic simulators, the experimental results, including the passive parasitic parameter analysis (AC resistance, inductance and capacitance) and scattering parameter analysis are presented. Discussions on the rise time, cross talk noise, and propagation delay for a 10 Gbit/s signal are also included.</abstract><pub>IEEE</pub><doi>10.1109/EMAP.2002.1188817</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 078037682X |
| ispartof | Proceedings of the 4th International Symposium on Electronic Materials and Packaging, 2002, 2002, p.83-88 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_1188817 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analytical models Bonding Clocks Electric resistance Electromagnetic analysis Electromagnetic induction Electromagnetic scattering Inductance Packaging Wire |
| title | High speed electrical performance comparison between bump with RDL and wire bond technologies |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T01%3A32%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=High%20speed%20electrical%20performance%20comparison%20between%20bump%20with%20RDL%20and%20wire%20bond%20technologies&rft.btitle=Proceedings%20of%20the%204th%20International%20Symposium%20on%20Electronic%20Materials%20and%20Packaging,%202002&rft.au=Chi-Tsung%20Chiu&rft.date=2002&rft.spage=83&rft.epage=88&rft.pages=83-88&rft.isbn=078037682X&rft.isbn_list=9780780376823&rft_id=info:doi/10.1109/EMAP.2002.1188817&rft_dat=%3Cieee_6IE%3E1188817%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1188817&rfr_iscdi=true |