Efficient field processing cores in an innovative protocol processor system-on-chip

We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a System-on-Chip that integrates variable size packet buffering, specialised cores for header and field processing, generic...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Lykakis, G., Mouratidis, N., Vlachos, K., Nikolaou, N., Perissakis, S., Sourdis, G., Konstantoulakis, G., Pnevmatikatos, D., Reisis, D.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	CMOS technology Data structures Hardware Pipelines Processor scheduling Protocols Prototypes Reduced instruction set computing System-on-a-chip Technological innovation
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!