Caches and hash trees for efficient memory integrity verification
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified program execution. A number of schemes are presented with different levels of integration between the on...
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| creator | Gassend, B. Suh, G.E. Clarke, D. van Dijk, M. Devadas, S. |
| description | We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified program execution. A number of schemes are presented with different levels of integration between the on-processor L2 cache and the hash-tree machinery. Simulations show that for the best of our methods, the performance overhead is less than 25%, a significant decrease from the 10/spl times/ overhead of a naive implementation. |
| doi_str_mv | 10.1109/HPCA.2003.1183547 |
| format | Conference Proceeding |
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| ispartof | The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings, 2003, p.295-306 |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application software Bandwidth Computer science Coprocessors Costs Hardware Laboratories Machinery Protection Security |
| title | Caches and hash trees for efficient memory integrity verification |
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