Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits
Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional C...
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Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2002-10, Vol.10 (5), p.566-581 |
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creator | Morgenshtein, A. Fish, A. Wagner, I.A. |
description | Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented. |
doi_str_mv | 10.1109/TVLSI.2002.801578 |
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This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2002.801578</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>Piscataway, NJ: IEEE</publisher><subject>Applied sciences ; Circuit design ; Circuit properties ; Circuit simulation ; Circuit synthesis ; CMOS technology ; Combinatorial analysis ; Delay ; Design engineering ; Design. Technologies. Operation analysis. Testing ; Digital ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Energy consumption ; Exact sciences and technology ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Logic circuits ; Logic design ; Power dissipation ; Propagation delay ; Semiconductor device measurement ; Semiconductor electronics. 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This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.</description><subject>Applied sciences</subject><subject>Circuit design</subject><subject>Circuit properties</subject><subject>Circuit simulation</subject><subject>Circuit synthesis</subject><subject>CMOS technology</subject><subject>Combinatorial analysis</subject><subject>Delay</subject><subject>Design engineering</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Energy consumption</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Logic circuits</subject><subject>Logic design</subject><subject>Power dissipation</subject><subject>Propagation delay</subject><subject>Semiconductor device measurement</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Transistors</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kUFr3DAQhU1JoMmmP6D0YgJJmoM3M5JtSbmFpNksLOSQtD0KWZZaLV7LkWRK_3293YVADpnLzDDfezC8LPuMMEcEcfX8Y_W0nBMAMueAFeMfsiOsKlaIqQ6mGWpacILwMTuOcQ2AZSngKPu5UMkUrbN2jM73ueuHMeVfF3fLy-tc5YP_Y0JhrHXamT7lG5N--za3PuSt--WS6nLtN43rVfLBbTcX9OhSPMkOreqi-bTvs-z7_bfn24di9bhY3t6sCk05TQXjFEzDOWlaBEShGiStKivFGoCmIXVtoaFItABec2EQa2iFIaotywopo7PsYuc7BP8ympjkxkVtuk71xo9RCmCiKhkpJ_L8XZJwShit6QSevgHXfgz99IUUhALlgm4h3EE6-BiDsXIIbqPCX4kgt4nI_4nIbSJyl8ikOdsbq6hVZ4PqtYuvwrIiomJk4r7sOGeMeT0j48CB_gN62ZJ2</recordid><startdate>20021001</startdate><enddate>20021001</enddate><creator>Morgenshtein, A.</creator><creator>Fish, A.</creator><creator>Wagner, I.A.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Operation analysis. Testing</topic><topic>Digital</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Energy consumption</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Logic circuits</topic><topic>Logic design</topic><topic>Power dissipation</topic><topic>Propagation delay</topic><topic>Semiconductor device measurement</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Transistors</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Morgenshtein, A.</creatorcontrib><creatorcontrib>Fish, A.</creatorcontrib><creatorcontrib>Wagner, I.A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Morgenshtein, A.</au><au>Fish, A.</au><au>Wagner, I.A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2002-10-01</date><risdate>2002</risdate><volume>10</volume><issue>5</issue><spage>566</spage><epage>581</epage><pages>566-581</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.</abstract><cop>Piscataway, NJ</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2002.801578</doi><tpages>16</tpages></addata></record> |
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subjects | Applied sciences Circuit design Circuit properties Circuit simulation Circuit synthesis CMOS technology Combinatorial analysis Delay Design engineering Design. Technologies. Operation analysis. Testing Digital Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Energy consumption Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Logic circuits Logic design Power dissipation Propagation delay Semiconductor device measurement Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transistors Very large scale integration |
title | Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits |
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