Fully depleted surrounding gate transistor (SGT) for 70 nm DRAM and beyond

Fully depleted surrounding gate transistor (SGT) for 70 nm DRAM and beyond

A high performance surrounding gate transistor (SGT) enabling sufficient static and dynamic retention time of future DRAM cells is presented. For the first time, we demonstrate a fully depleted SGT, that shows no reduction of the retention time due to the transient bipolar effect. This effect potent...

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Hauptverfasser: Goebel, B., Lutzen, J., Manger, D., Moll, P., Mummler, K., Popp, M., Scheler, U., Schlosser, T., Seidl, H., Sesterhenn, M., Slesazeck, S., Tegen, S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied sciences
Capacitors
Design. Technologies. Operation analysis. Testing
Doping
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Leakage current
MOSFETs
Oxidation
Random access memory
Scalability
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
Space charge
Testing
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Beschreibung
Zusammenfassung:A high performance surrounding gate transistor (SGT) enabling sufficient static and dynamic retention time of future DRAM cells is presented. For the first time, we demonstrate a fully depleted SGT, that shows no reduction of the retention time due to the transient bipolar effect. This effect potentially prevents DRAM application of fully depleted SGTs and is therefore investigated in detail. Based on experimental results, the impact of the proposed SGT on the scalability and performance of future DRAMs is discussed.
DOI:10.1109/IEDM.2002.1175831