Architecture and design of a pseudo two-port VLSI snoopy cache memory

A CMOS VLSI cache memory subsystem that includes a 72 K-bit cache memory, an 11 K-bit tag memory, a 1.3 K-bit state array, two special buffers and cache control logic, has been designed and integrated on a microprocessor chip. The architecture, design and analysis of the cache design are presented....

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Chuang, S.C.-M., Bruss, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Cache memory Central Processing Unit CMOS process Delay Logic arrays Logic design System buses System performance System-on-a-chip Very large scale integration
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